FAIRCHILD FOUNDRY SERVICES AGREEMENT CONFIDENTIAL PORTIONS OF THIS DOCUMENT HAVE BEEN DELETED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION PURSUANT TO A REQUEST FOR CONFIDENTIAL TREATMENT. THIS FAIRCHILD FOUNDRY SERVICES AGREEMENT ("Agreement") is dated and made effective this 11th day of March, 1997 (the "Effective Date") by and between NATIONAL SEMICONDUCTOR CORPORATION, a Delaware corporation, having its principal place of business at 2900 Semiconductor Drive, Santa Clara, California 95052-8090 ("National") and FAIRCHILD SEMICONDUCTOR CORPORATION, a Delaware corporation, having its principal place of business at 333 Western Avenue, South Portland, Maine 04106 ("Fairchild"). National and/or Fairchild may be referred to herein as a "Party" or the "Parties" as the case may require. WITNESSETH: WHEREAS, the Parties have entered into a certain Asset Purchase Agreement (hereinafter referred to as the "Purchase Agreement") under which Fairchild is acquiring certain of the assets of National's Logic, Memory and Discrete Power and Signal Technologies Business Units as historically conducted and accounted for (including Flash Memory, but excluding Public Networks, Programmable Products and Mil/Aero Logic Products) (the "Business"); and WHEREAS, pursuant to the transactions contemplated in the Purchase Agreement, Fairchild is acquiring National's manufacturing facilities in South Portland, Maine (excluding the eight-inch fab and related facilities); West Jordan, Utah; and Penang, Malaysia, and Cebu, the Philippines; and WHEREAS, after the closing of the transactions contemplated by the Purchase Agreement Fairchild will own and operate the Facilities; and WHEREAS, National, using proprietary processes, has been manufacturing silicon wafers containing certain integrated circuits at the Facilities; and WHEREAS, National is conveying to Fairchild certain intellectual property rights pursuant to the Technology Licensing and Transfer Agreement between National and Fairchild, of even date herewith; and WHEREAS, National and Fairchild desire to enter into an agreement under which Fairchild will continue to provide certain manufacturing services to National following the closing of the transactions contemplated by the Purchase Agreement; and WHEREAS, National and Fairchild recognize that the prices National shall pay to Fairchild for silicon wafers manufactured pursuant to this Agreement are determined based on the collateral transactions and ongoing relationship between the Parties as expressed in the Purchase Agreement, Revenue Side Letter between National and Fairchild of even date herewith (the "Revenue Side Letter") and the other Operating Agreements (as defined in Paragraph 7.1); and WHEREAS, the execution and delivery of this Agreement is a condition precedent to the closing of the transactions contemplated by the Purchase Agreement. NOW, THEREFORE, in furtherance of the foregoing premises and in consideration of the mutual covenants and obligations hereinafter set forth, the Parties hereto, intending to be legally bound hereby, do agree as follows: 1.0 DEFINITIONS 1.1 "Acceptance Criteria" shall mean the electrical parameter testing, process control monitor ("PCM") and other inspections for each Product and/or Process as set forth in Exhibit F hereto, all of which are to be performed by Fairchild prior to shipment of Wafers hereunder. 1.2 "Best Efforts" shall require that the obligated Party make a diligent, reasonable and good faith effort to accomplish the applicable objective. Such obligation, however, does not require any material expenditure of funds or the incurrence of any material liability on the part of the obligated Party, which expenditure or liability is unreasonable in light of the related objective, nor does it require that the obligated Party act in a manner which would otherwise be contrary to prudent business judgment or normal commercial practices in order to accomplish the objective. The fact that the objective is not actually accomplished is no indication that the obligated Party did not in fact utilize its Best Efforts in attempting to accomplish the objective. 1.3 "Confidential Information" shall have the meaning set forth in Paragraph 16.1 below. 1.4 "Effective Date" shall mean the date first set forth above. -2- 1.5 "Equivalent Wafers" for wafers manufactured at the South Portland, Maine six inch fab shall mean the actual number of wafers in a given Process multiplied by the process complexity factor for that Process, as set forth in Exhibit A hereto; and for wafers manufactured in a four or five inch fab, Equivalent Wafers shall mean the number of six inch equivalent wafers. 1.6 "Facilities" shall mean the existing wafer fabrication facilities located at South Portland, Maine (excluding the eight inch fabrication facility of which National is retaining ownership) and West Jordan, Utah, transferred to Fairchild from National pursuant to the Purchase Agreement. 1.7 "Fairchild" shall mean Fairchild Semiconductor Corporation and its Subsidiaries. 1.8 "Fairchild Assured Capacity" shall mean the capacity that Fairchild agrees to supply National pursuant to Section 5 below. 1.9 "Masks" shall mean the masks and reticle sets, including the mask holders and ASM pods, for the Products and Wafers used to manufacture Products hereunder. 1.10 "National" shall mean National Semiconductor Corporation and its Subsidiaries. 1.11 "Processes" shall mean those National proprietary wafer manufacturing processes and associated unit processes to be used in the fabrication of Wafers hereunder which are set forth in Exhibit A hereto, as such processes shall be modified from time to time as agreed in writing by the Parties. 1.12 "Products" shall mean National's integrated circuit products which will be manufactured by Fairchild in wafer form for National hereunder and which are identified by National's part numbers listed in Exhibit B hereto, which exhibit may be amended from time to time as the parties may agree. 1.13 "Quality and Reliability Criteria" shall mean National's manufacturing process quality and reliability specifications, as set forth in the revision of National Specification CP0008 which is in effect as of the Effective Date, and which are to be followed -3- by Fairchild in manufacturing Wafers hereunder. 1.14 "Specifications" shall mean the technical specifications (such as Mask ID, Process Flow and Sort/Test) as listed in Exhibit B for each of the Products as provided in this Agreement. 1.15 "Subsidiary" shall mean any corporation, partnership, joint venture or similar entity more than fifty (50%) owned or controlled by a Party hereto, provided that any such entity shall no longer be deemed a Subsidiary after such ownership or control ceases to exist. 1.16 "Technology Licensing and Transfer Agreement" shall mean the agreement of even date herewith between the Parties under which National is licensing and transferring certain intellectual property rights to Fairchild. 1.17 "Wafers" shall mean four-inch (4"), five-inch (5") and/or six-inch (6") silicon wafers for any of the Products to be manufactured by Fairchild hereunder. 1.18 "Wafer Module" shall mean the Fairchild four-inch (4"), five-inch (5"), and six-inch (6") wafer fabrication units in South Portland, Maine and the six-inch (6") wafer fabrication unit in West Jordan, Utah. 2.0 INTELLECTUAL PROPERTY/NON-COMPETE 2.1 The provisions of the Technology Licensing and Transfer Agreement will govern all issues related to the respective intellectual property rights of the Parties hereunder, to include but not be limited to, use rights, ownership rights and indemnification obligations. 2.2 All manufacturing of Wafers shall take place at the Facilities. Fairchild shall not transfer any National-owned intellectual property or technical information outside of the Facilities or to any other site, other than as may be permitted under the Technology Licensing and Transfer Agreement. 2.3 During the term of this Agreement, including all extensions hereto and any subsequent ramp-down period provided under Paragraph 15.1, Fairchild will not develop, manufacture (except for National hereunder), market or sell any integrated circuit that has -4- substantially the same specifications as any Product. 3.0 PROCESSES 3.1 Exhibit A lists the Processes which Fairchild shall use in manufacturing Wafers hereunder for National. Exhibit A may be amended from time to time by mutual agreement in writing of the Parties, as new processes are developed and older Processes become obsolete. 3.2 After qualification is successfully completed for any Product to be manufactured under this Agreement, if Fairchild desires to make material Process changes affecting form, fit or function, Fairchild will notify National of the intended change in accordance with Fairchild's process change procedures then in effect. If the proposed changes are unacceptable to National, National and Fairchild shall work together in efforts to resolve the problem and qualify the changed Process for making Wafers. If during the first thirty-nine (39) fiscal periods of this Agreement the Parties are unable to resolve the problem, Fairchild shall continue to run the unmodified Process to supply Wafers pursuant to this Agreement. After the first 39 fiscal periods of this Agreement, if the Parties are unable to resolve the problem, Fairchild shall have the right to make such Process changes upon the provision of ninety (90) days prior written notice to National. 3.3 Should Fairchild elect to discontinue a Process, it must give National written notice of no less than twenty-four (24) fiscal periods prior to the date it intends to discontinue any Process in the ABiC family and written notice of no less than twelve (12) fiscal periods for any other Process, or its future amended form. In no event, however may Fairchild discontinue any Process during the first thirty-nine (39) fiscal periods of this Agreement unless National agrees. Subsequent to Fairchild's notice of Process discontinuance, Fairchild will make provisions with National for Last Time Buys, and commit to ship all Wafers requested in such Last Time Buys as the Parties may negotiate. If Fairchild is unable to deliver Wafers due to a Process discontinuance during any ramp down phase occurring after the first 39 fiscal periods, then any ramp-down revenue obligations of National associated -5- with Wafers to be manufactured under that Process will be discharged in full. 3.4 National shall have the right, in its sole discretion, to establish an alternative source of manufacturing for any Process. In support of any Process transfer required to establish such alternate source, Fairchild shall make available to National process characterization data, where such data exists at the time of such request, and all applicable manufacturing specifications, including run cards and complete unit process specifications for the Processes. In further support of such transfer, National may contract with Fairchild, at a cost to be negotiated, for up to thirteen (13) man weeks of engineering services. If such services are required away from the Facilities, National shall also pay reasonable travel and per diem expenses for the Fairchild engineers providing such services. 3.5 There are currently a number of Processes under development at the Facilities. Attached as Exhibit C hereto is a listing of said Processes, the timetable and milestones to completion for each and the funding which National shall pay Fairchild for such development services. Fairchild will utilize its Best Efforts to complete all development work successfully in accordance with Exhibit C. National may terminate such development services prior to completion thereof only after three (3) months prior written notice to Fairchild. The rights of the Parties to any intellectual property resulting from such development work shall be governed by the terms of the Technology Transfer and License Agreement. 4.0 EXISTING PRODUCTS; SET UP AND QUALIFICATION OF NEW PRODUCTS; MODIFICATION OF EXISTING PRODUCTS 4.1 For each new Product that National proposes to have Fairchild manufacture, National will provide to Fairchild in advance the Specifications and design layout of the Product for review and comment by Fairchild. The Parties will also agree on the Acceptance Criteria, including electrical test parameters, and Quality and Reliability Criteria for the prototype Wafers to be manufactured for the new Product during the qualification process. 4.2 An initial data base for Mask generation or pattern generation, or acceptable production Masks will be -6- provided by National to Fairchild, per Fairchild specifications for large die, at National's expense, for each new Product to be fabricated for National. In the alternative, National may provide Fairchild with prime die design data and Fairchild will provide the frame and fracture services and procure the Mask set at National's expense. After receipt of the initial data base, or pattern generation tape, or master or sub-master Mask set, additional and/or replacement Mask sets shall be the responsibility and expense of Fairchild. All such data bases, pattern generation tapes and Mask sets shall be the property of National, regardless of whether they were initially supplied by National or replaced by Fairchild. 4.3 As soon as practical following agreement on the items in Paragraph 4.1 above, and following receipt of a written purchase order from National, Fairchild will begin manufacture of twelve (12) prototype Wafers for such Product as is specified in the purchase order. Fairchild will perform the electrical testing specified in the initial Acceptance Criteria and supply the test data to National with the prototype Wafers. Fairchild's obligation shall be limited to providing Wafers that meet the applicable PCM specifications and the associated test data. National will promptly inspect the prototype Wafers and notify Fairchild in writing of the results. If the prototype Wafers do not meet the Acceptance Criteria and Quality and Reliability Criteria, the Parties will cooperate in good faith to determine the reason for such failure. 4.4 In connection with the completion of the qualification process for any new Product, National will deliver to Fairchild final Specifications for the Product incorporating any changes agreed in writing by the Parties during the qualification process. The Parties will also negotiate for each Product the final Acceptance Criteria and Quality and Reliability Criteria to be used for the commercial production lots of Wafers. 4.5 Unless otherwise agreed in writing, production quantities of Wafers of a new Product will not be manufactured prior to completion of the qualification process under this Section 4. In the event that National desires for Fairchild to manufacture production quantities, the Parties will agree in writing on the terms before Fairchild accepts the purchase -7- order. 4.6 If either National or Fairchild desires to make any changes to the final Specifications, Acceptance Criteria or Quality and Reliability Criteria for any existing Product, that Party shall notify the other Party in writing and negotiate the changes in good faith, including any changes in prices required by such modifications. A modification to any of the foregoing will be binding only when a writing to which such modification is attached has been signed by both Parties as provided in this Agreement. The Parties will separately negotiate the price and terms of any prototype Wafers required in connection with such change. 4.7 Fairchild may at its discretion declare a Product obsolete if such Product has not been run in production for a minimum of six (6) fiscal periods. Fairchild must provide National with twelve (12) months prior written notice of an obsolescence declaration and make reasonable provisions with National for a Last Time Buy for such Product. Within thirty (30) days after completing production of National's Last Time Buy, Fairchild shall return all data bases and Masks for such Product to National. 5.0 CAPACITY; VOLUME COMMITMENTS; PRODUCTION PLANNING 5.1 All planning herein will be done under National's accounting calendar which currently divides its fiscal year into four (4) equal fiscal quarters, each of which consists of three (3) fiscal periods. The first two (2) periods of each quarter are of four (4) weeks in duration and the third period is of five (5) weeks duration. 5.2 Two (2) weeks prior to the end of each National fiscal period National will provide in writing to Fairchild a baseline quantity of Wafers, set forth in terms of Wafer starts per Wafer Module, for the next eight (8) fiscal periods (the "Capacity Request"). For the South Portland, Maine facility the Capacity Request shall clearly state each Wafer in terms of 6" Equivalent Wafers. Equivalency factors are set forth in Exhibit A. For the West Jordan, Utah facility the Capacity Request shall be stated in terms of the Process required to manufacture the Wafers. National's initial Capacity Request and Fairchild's -8- Assured Capacity response formats are set forth in Exhibit D. 5.3 Each fiscal period National may change the Capacity Request in accordance with the following table, provided that the maximum Capacity Request for each Wafer Module does not exceed National's share of each Wafer Module's installed equipment capacity as provided herein. Any changes outside those permitted under the following table must be by written agreement of the Parties. Fiscal Periods in the Capacity Request Permitted Changes -------------------- ----------------- Period 1 Fixed Period 2 +/-10% Period 3 +/-15% Period 4 +/-20% Period 5 +/-25% Period 6 +/-30% Period 7 +/-35% Period 8 +/-40% 5.4 National's share of a Wafer Module's installed equipment capacity will equal the previous Fairchild Assured Capacity for that Wafer Module, plus that percentage of any excess capacity available in the Wafer Module equal to National's percentage of the currently utilized capacity in said Wafer Module. Installed equipment capacity by Wafer Module in South Portland, Maine is set forth below: Wafer Module Annual Capacity ------------ --------------- FM Class 1 6" 133,000 Equivalent Wafer starts FM Class 100 4" 180,000 Wafer starts (6" equivalent) FM Class 100 5" 110,000 Wafer starts (6" equivalent) As no excess capacity exists in West Jordan, Utah, Fairchild hereby commits the following capacities to National for each National fiscal year: FY 1998 19,400 Wafer starts FY 1999 7,000 Wafer starts FY 2000 0 Wafer starts -9- 5.5 One (1) work week after receipt of the Capacity Request, Fairchild shall provide National with a response to such Capacity Request, the "Fairchild Assured Capacity". The Fairchild Assured Capacity must guarantee the amount requested in National's latest Capacity Request, provided that any changes to National's latest Capacity Request are within the limits of Paragraph 5.3. Fairchild shall utilize its Best Efforts to comply with any requests by National for capacity above those which are permitted under Paragraph 5.3. In any case, Fairchild shall be obligated hereunder to provide National with the Wafer starts guaranteed in the Fairchild Assured Capacity response. The initial Fairchild Assured Capacity response will be the last one provided prior to the Effective Date. Set forth below are two examples of the foregoing: Example #1 The new Capacity Request is less than the last Fairchild Assured Capacity response. Period A B C D E F G H ------ - - - - - - - - Last Capacity Request 100 100 100 100 100 100 100 100 Last Fairchild Assured Capacity 100 100 100 100 100 100 100 100 New Capacity Request 100 90 85 80 75 70 65 65 New Fairchild Assured Capacity 100 90 85 80 75 70 65 65 Example #2 The new Capacity Request is greater than the last Fairchild Assured Capacity response. Period A B C D E F G H ------ - - - - - - - - Last Capacity Request 100 100 100 100 100 100 100 100 Last Fairchild Assured Capacity 100 100 100 100 100 100 100 100 New Capacity Request 100 110 115 120 125 130 135 135 New Fairchild Assured Capacity 100 110 115 120 125 130 135 135 5.6 The timetable for the rolling eight fiscal period Capacity Request, the Fairchild Assured Capacity response, purchase order release and detailed device level Wafer starts request for the next fiscal period are set forth in Exhibit D hereto. 6.0 PURCHASE ORDERS 6.1 All purchases and sales between Fairchild and National shall be initiated by National's issuance of written purchase orders sent by either first class mail or facsimile. By written agreement of the Parties, purchase orders may also be sent and -10- acknowledged by electronic data exchange or other mutually satisfactory system. Such "blanket" purchase orders shall be issued once per fiscal quarter for Wafers to be delivered three (3) fiscal periods in the future. They shall state the Wafer quantities (specifying whether equivalents or actual) by Wafer Module, and shipping and invoicing instructions. Fairchild shall accept purchase orders through a written or electronic acknowledgment. Within a reasonable time after receipt of National's detailed device level Wafer starts request for the next fiscal period, Fairchild shall provide National with a Product delivery schedule either on a weekly basis as the Wafers are started or for the Wafer starts for the entire fiscal period, as the parties may agree in writing. The purchase orders may utilize the first three (3) fiscal periods forecast in the eight period rolling forecast supplied pursuant to Section 5, as the embodiment of the purchase order for specifying the Wafer quantity by Wafer Module and Process, and whether sorted or unsorted. 6.2 In the event of any conflict between the terms and conditions of this Agreement and either Party's purchase order, acknowledgment, or similar forms, priority shall be determined as follows: (a) typewritten or handwritten terms on the face of a written purchase order, acknowledgment or similar document or in the main body of an electronic equivalent which have been specifically accepted in writing by the other Party's Program Manager; (b) the terms of this Agreement; (c) preprinted terms incorporated in the purchase order, acknowledgment or similar document. 6.3 Consistent with standard practices of issuing specific device level details of part numbers to be fabricated on a weekly or periodic basis, National may unilaterally change the part number to be manufactured, provided that Fairchild agrees that the change does not negatively impact Fairchild's loadings and provided further that there is no change in the Process flow to be used. A change that will negatively impact loading or alter the Process flow may only be directed upon Fairchild's written -11- agreement, which shall utilize its Best Efforts to comply with such requested change. The specific part number detail shall be submitted by first class mail or facsimile. By written agreement of the Parties, specific part number detail may also be sent by electronic data exchange, or other mutually satisfactory system. 6.4 National shall request delivery dates which are consistent with Fairchild's reasonable lead times for each Product as indicated at the time National's purchase order is placed. Notwithstanding the foregoing, Fairchild shall utilize its Best Efforts to accommodate requests by National for quick turnarounds or "hot lots", which includes prototype lots. Hot lot cycle times and the premiums to be paid therefor are listed in Exhibit K. 6.5 Fairchild may manufacture lots of any size which satisfy the requirements of effective manufacturing. However, National must place orders for full flow and prototype Products in increments of twelve (12) or twenty-four (24) Wafers. For personalized ASIC Wafers drawn from mid-flow inventories, the smallest quantity that shall be ordered by National is three (3) Wafers, except for Wafers manufactured in the five-inch (5") fab, in which case the smallest quantity that can be ordered is six (6) Wafers. 7.0 PRICES AND PAYMENT 7.1 The Parties hereby acknowledge that, as part of the collateral transactions contemplated under the Purchase Agreement and ongoing relationship between the Parties they have entered into the Revenue Side Letter under which National has agreed to provide a minimum revenue of [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] periods after the Effective Date. National shall discharge its obligations under the Revenue Side Letter by purchasing goods and services under this Agreement, a corresponding Fairchild Assembly Services Agreement, and a Mil/Aero Wafer and Services Agreement of even date herewith (collectively the "Operating Agreements"). Set forth herein at Exhibit N is the forecasted volume of Wafers, by Wafer Module and Process, that National will purchase from Fairchild during the -12- aforementioned thirty-nine fiscal periods (the "Forecast Volumes"). The Forecast Volumes are for pricing purposes under this Section 7 only and may vary in magnitude and mix in practice, whereupon the prices applicable to the revised magnitude and mix may also vary. The Forecast Volumes will be reviewed and updated by the Parties every [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] fiscal periods and shall be consistent with the principles of manufacturing set forth in Exhibit O. 7.2 Set forth in Exhibit N hereto are the prices which National shall pay to Fairchild for Wafers manufactured hereunder during the first [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] fiscal periods of this Agreement. The prices in Exhibit N for fiscal periods [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] are for information purposes only and are based on the Parties' best estimate of projected volumes and costs. Set forth herein at Exhibit M is the forecast capacity utilization and associated fixed costs of the Fairchild FM 6001 six-inch fab by both National and Fairchild for the term of this Agreement. 7.3 The prices which National shall pay to Fairchild for Wafers manufactured hereunder after the first [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] periods of this Agreement shall be determined as set forth herein in Exhibit L. The pricing methodology to be followed hereunder will depend on the Wafer Module in which the Wafers are being manufactured. In addition, Products that qualify will be subject to a die cost adjustment as provided in Exhibit E. 7.4 For purposes of Exhibit L, National, or any "Big 6" accounting firm designated by National, shall have reasonable rights to audit not more than twice each fiscal year the books and records of Fairchild relevant to the pricing terms of this Agreement in order to come to agreement with Fairchild with regard to Fairchild's actual manufacturing costs. 7.5 Prices are quoted and shall be paid in U.S. Dollars. Such prices shall be on an FOB ship point basis. Payment terms are net thirty (30) from date -13- of invoice. Miscellaneous services may be invoiced separately. 7.6 National shall pay, in addition to the prices quoted or invoiced, the amount of any freight, insurance, special handling and duties. National shall also pay all sales, use, excise or other similar tax applicable to the sale of goods or provision of services covered by this Agreement, or National shall supply Fairchild with an appropriate tax exemption certificate. 7.7 National shall in no event be required to pay prices in excess of those charged by Fairchild for other third party foundry customers, for substantially similar products sold on substantially similar terms (e.g., volume, payment terms, manufacturing criteria, contractual commitments vs. spot buys, etc.). In the event Fairchild desires to perform such foundry services for other third party customers at such lower prices, Fairchild shall immediately notify National and National shall begin receiving the benefit of such lower price at the same time as such other third party customer. This Paragraph 7.7 shall not apply to the prices to be paid by National hereunder for the first twelve (12) fiscal periods of this Agreement, or if National fails to honor its fixed commitments under Section 5 and to the extent that such sales by Fairchild to third party foundry customers are only made in an attempt to make up for any underutilization of capacity thereby caused by National. 8.0 OTHER MANUFACTURING SERVICES 8.1 At National's request, Fairchild will perform Wafer sort and test services based on sort and test programs prepared, owned and otherwise proprietary to National. Towards that end, National shall supply Fairchild with National-owned specific probe cards, load boards and test software in order that Fairchild may provide such services. Wafer sort shall be priced by hours of active sorting, with specific prices as set forth in Exhibit G, and specific sort times as set forth in Exhibit B. 8.2 At National's request, Fairchild will perform separate epitaxial deposition services for National for -14- Wafers not otherwise manufactured by Fairchild hereunder. The general principles set forth in Sections 5 and 6 above shall apply to such services, with epitaxial deposition services being treated as a separate Wafer Module with its respective Capacity Request and Fairchild Assured Capacity, but the lead time for epitaxial deposition shall be one (1) fiscal period. Prices shown in Exhibit N for Wafer foundry services include epitaxial deposition where appropriate. Otherwise, prices for such services are set forth in Exhibit G. 8.3 At National's request, Fairchild shall continue to provide certain ongoing operational support services (the "Miscellaneous Support Services") to National at the same level of support that was in effect as of the Effective Date as listed in Exhibit J hereto consisting of: (i) those services which will be provided to National at no charge; and (ii) those services which will be provided at the prices set forth in Exhibit J on a purchase order basis. Operational support services not shown in Exhibit J will be provided on a purchase order basis at prices to be negotiated by the Parties case-by-case. 8.4 In support of the Processes and those manufacturing processes listed in Exhibit C, Fairchild will make available design support information including the following items: (a) Layout design rules. (b) Industry standard models for active devices (BSIM3v3 for CMOS devices and Gummel-Poon with parasitics for bipolar devices) representing nominal conditions and performance corners. (c) Industry standard models, as stated in the National NTPRS document in effect as of the Effective Date, for parasitic elements, such as interconnect resistances and capacitances, sheet resistivities of all conducting layers, parasitic capacitances for diffused areas, and so forth, including additional elements or devices intended for mixed-signal applications. (d) Process cross sections, if not already available at National. -15- (e) Sufficient sizing and PCM information to assure the integrity of Masks ordered in support of Products to be manufactured. (f) Yield models plus applicable current and forecast parameters such as Ys and Do for those models. This information should be in the form of at least one controlled paper copy or electronic access to a controlled copy. National, at its discretion, may request a controlled electronic copy of the required information in lieu of the paper copy. Fairchild will provide the foregoing services at no charge to National, limited to those engineering services performed as of the Effective Date. Any additional requests are subject to fees set forth in Exhibit J. 9.0 DELIVERY; RESCHEDULING AND CANCELLATION 9.1 Fairchild shall make reasonable and diligent efforts to deliver Wafers on the delivery dates specified in the Product delivery schedule provided by Fairchild pursuant to Paragraph 6.1. Any shipment made within fifteen (15) days before or after the shipment date(s) specified in said Product delivery schedule shall constitute timely shipment. Partial shipments will be allowed and may be invoiced separately. A delivery will be considered conforming if it contains a quantity equal to plus or minus five percent (5%) of the quantity ordered. 9.2 If Fairchild has not made shipment of Products within fifteen (15) days after the shipment date specified in the Product delivery schedule provided by Fairchild pursuant to Paragraph 6.1, National shall have the right, subject to Paragraph 19.2, to cancel that portion of its purchase order pertaining to such Products, but only in the event that National's customer for those Products has cancelled its order with National for such Products. Notwithstanding the foregoing, if Fairchild has not made shipment of Products within thirty (30) days after the shipment date specified in the Product delivery schedule, National shall have the right, subject to Paragraph 19.2, in its -16- sole discretion, to cancel that portion of its purchase order pertaining to such Products, regardless of whether National's customer has cancelled its order with National or not. In either event, any obligation of National under its Capacity Request and/or any commitment to Fairchild under the Revenue Side Letter associated with such cancelled purchase order shall be discharged in full and National shall have no liability whatsoever to Fairchild therefore. 9.3 All Wafers delivered pursuant to the terms of this Agreement shall be suitable, packed for shipment in Fairchild's standard containers, marked for shipment to National's address set forth in the applicable purchase order and delivered to a carrier or forwarding agent chosen by National. Should National fail to designate a carrier, forwarding agent or type of conveyance, Fairchild shall make such designation in conformance with its standard shipping practices. Shipment will be F.O.B. shipping point, at which time risk of loss and title shall pass to National. Shipments will be subject to incoming inspection as set forth in Paragraph 10.2 below. 9.4 To facilitate the inspection of Product deliveries to National, lot integrity shall be maintained on all such deliveries, unless specifically waived by mutual agreement of the Parties. 9.5 Subject to the provisions of Section 6, National may cancel any purchase order upon at least one (1) week's notice prior to the commencement of manufacturing without charge, provided that National reimburses Fairchild for the cost of any unique raw materials purchased for such order. 9.6 National may request that Fairchild stop production of Wafers in process for National's convenience and Fairchild shall consider stopping depending on the point of process. In such event, National shall pay for all Wafers at the agreed price, subject to a negotiated adjustment based upon the degree of completion of the Wafers and whether or not Fairchild is able to utilize the unfilled capacity. Fairchild will, if reasonably practicable, restart production of stopped Wafers one time within a reasonable time after receipt of a written request from National, subject to National's payment of any -17- additional expenses incurred. Sections 10, 11 and 12 of this Agreement shall not apply to Wafers stopped under this Paragraph 9.6 for more than thirty (30) days, nor shall Fairchild make any commitments of yield with respect to such Wafers. 9.7 In the event that National elects to maintain an inventory of partially finished Wafers, ownership of the partially finished Wafers will pass to National when they reach the holding point defined by the relevant Process flow. Fairchild will invoice National for such Wafers, but they will be stored under clean-room conditions and remain in the Wafer processing WIP management system. Fairchild will inform National of the number and types of these Wafers remaining in inventory at the end of each fiscal period. Further, the electronic records and physical inventory shall be available for inspection by National at any time. Fairchild shall credit National with the amount previously invoiced for any such Wafers at such time as they are restarted in the Process flow. 9.8 As of 12:01 A.M. on the Effective Date, National will own all Wafers located at the Facilities which Fairchild has commenced processing but which have not yet been completed in accordance with the pertinent Process flow. Unless expressly directed in writing by National otherwise, Fairchild shall continue to process each Wafer to a normal state of completion in the applicable Wafer Module. National shall pay Fairchild for the accumulated additional processing costs, plus a twenty-five percent (25%) mark up, for the additional processing taking place on and after the Effective Date. The provisions of Sections 10, 11 and 12 hereof shall specifically apply to all such Wafers. 10.0 QUALITY CONTROL AND INSPECTION; AND RELIABILITY 10.1 Fairchild will manufacture Wafers in accordance with the Quality and Reliability Criteria for the applicable Product. Prior to shipment, Fairchild will perform the electrical parameter testing and other inspections specified to be performed by it in the applicable Acceptance Criteria on each Wafer lot manufactured. Fairchild will only ship those Wafer lots that successfully pass the applicable Acceptance Criteria. Fairchild will -18- electronically provide National with the electrical test data specified in the applicable Acceptance Criteria. Wafers will be laser scribed with lot and wafer number for statistical monitoring and lot number traceability. 10.2 National shall promptly provide for inspection and testing of each shipment of Wafers upon receipt in accordance with the Acceptance Criteria and shall notify Fairchild in writing of acceptance of the Wafers. If National has not given written notice to Fairchild of rejection of all or part of a shipment within thirty (30) days of receipt, National will be deemed to have accepted such Wafers. In the event any lot or Wafer is found to fail the Acceptance Criteria prior to final acceptance, National shall promptly return it to Fairchild, together with all test data and other information reasonably required by Fairchild. Upon confirmation by Fairchild that such Wafers fail the Acceptance Criteria, Fairchild shall replace such lot or Wafer on a timely basis. 10.3 National shall promptly provide for yield probe tests to be conducted on the Wafers and communicate the results of the tests to Fairchild within thirty (30) days of receipt of Wafers from Fairchild. The right to return any Wafers for low yield shall be governed by Section 11 below. 10.4 MPS-3-000 (Material Procurement Specification) - General Provisions and Quality Requirements for External (Non-National) Wafer Fab Facilities and MPS-3-001 (Material Procurement Specification) - Technical Requirements for CMOS Processing are the National policies for the purchase of integrated circuits from independent suppliers. These policies as in effect at the Effective Date shall provide criteria for the initial and continuing qualification of the Facilities and evaluation of Wafers manufactured by Fairchild hereunder. To the extent that those policies are not inconsistent with the provisions of this Agreement, National shall not be required to accept delivery of any Wafers hereunder if Fairchild fails to comply with said policies or such other similar policies as may be mutually agreed to in writing by the Parties. 10.5 Fairchild hereby warrants that the South Portland, Maine Facility currently is, and will remain -19- throughout the term of this Agreement, ISO9000 certified. Fairchild further warrants that the West Jordan, Utah Facility currently is, and will remain throughout the term of this Agreement, ISO9000 and AEC-100 certified. 11.0 MINIMUM YIELD ASSURANCES 11.1 Fairchild will guarantee a minimum yield assurance ("MYA") on a per Product basis for those Wafers fabricated and probed by Fairchild. For Wafers not sorted by Fairchild the MYA limits will apply only to Wafers whose substandard yield is caused by materials or Fairchild's workmanship. MYAs shall function as a reliability screen hereunder for maverick Wafers, via standard sort test results and yield. 11.2 The baseline yield and initial MYA for each Product to be manufactured by Fairchild hereunder is set forth in Exhibit B hereto. 11.3 For a new Product, the baseline yield and MYA will be established after a minimum of twenty (20) Wafer lot runs have been tested to production released test programs. A new baseline yield and MYA will be calculated whenever National makes any modifications to said test programs. 11.4 For Products that qualify for die cost sharing, as provided in Exhibit E, the baseline Net Die Per Wafer (NDPW) for the Product will be used for defining the MYA. For all other Products, each fiscal quarter, each Product's baseline yield will be calculated using the previous fiscal quarter's results, or the previous twenty (20) Wafer lot runs if less than twenty (20) Wafer lot runs were processed in said previous quarter. The mean and standard deviation (sigma) yield for a Product, will be calculated using individual Wafer data. Zero yielding Wafers will be excluded from such calculations. The results of such calculations will be used in defining the MYA for that Product for the quarter in which the calculations are made, but only if the mean yield changes by more than +/- 2%. 11.5 MYA will be determined as follows. For purposes of Wafers manufactured in South Portland, Maine, -20- Wafers which yield less than sixty (60%) percent of the mean will be considered discrepant and may be returned for full credit at National's discretion. For purposes of Wafers manufactured in West Jordan, Utah, Wafers which yield less than mean minus six sigma, as determined according to National Specification SS4908 in the version extant as of the Effective Date, will be considered discrepant and may be returned for full credit at National's discretion. In no event shall Fairchild accept returns of Wafers on non-released products. 11.6 National shall provide yield analysis information on Wafers returned to Fairchild under this Section 11, in order to assist Fairchild in continuous Process improvement. 11.7 In the event of an extended period of substandard yields on a Product, Fairchild will utilize its Best Efforts to correct any Process related causes and the Parties will negotiate in good faith to make up for the Process related yield loss experienced by National and its customers. 12.0 WARRANTY 12.1 Fairchild warrants that the Wafers delivered hereunder shall meet the Quality and Reliability Criteria and shall be free from defects in material and Fairchild's workmanship under normal use for a period of one (1) year from the date of delivery. If, during the one year period: (i) Fairchild is notified in writing promptly upon discovery with a detailed description of any such defect in any Product (at which time Fairchild shall issue a return material authorization number to National), and; (ii) National returns such Product to the applicable Facility at National's expense for inspection; and (iii) Fairchild's examination of such Product reveals that the Product is indeed defective and does not meet the applicable Quality and Reliability Criteria or is defective in materials or Fairchild's workmanship and such problems are not caused by accident, -21- abuse, misuse, neglect, improper storage, handling, packaging or installation, repair, alteration or improper testing or use by someone other than Fairchild then, within a reasonable time, Fairchild, at its sole option, shall either replace or credit National for such defective Product. Fairchild shall return any Products replaced under this warranty to National, transportation prepaid, and shall reimburse National for the transportation charges paid by National in returning such defective Products to Fairchild. 12.2 THE FOREGOING WARRANTY CONSTITUTES FAIRCHILD'S EXCLUSIVE LIABILITY, AND NATIONAL'S EXCLUSIVE REMEDY, FOR ANY BREACH OF WARRANTY. EXCEPT AS SET FORTH HEREIN, FAIRCHILD MAKES AND NATIONAL RECEIVES NO WARRANTIES OR CONDITIONS ON THE PRODUCTS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND FAIRCHILD SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. 13.0 ON-SITE INSPECTION AND INFORMATION 13.1 Fairchild shall allow National and/or National's customers to visit and evaluate the Facilities during normal business hours as part of established source inspection programs, it being understood and agreed between National and Fairchild that National must obtain the concurrence of Fairchild for the scheduling of all such visits, which such concurrence shall not be unreasonably withheld. It is anticipated that such visits will occur no more than once per quarter on average. 13.2 Upon National's written request, Fairchild will provide National with process control information, to include but not be limited to: process and electrical test yield results, current process specifications and conformance to specifications; calibration schedules and logs for equipment; environmental monitor information for air, gases and DI water; documentation of operator qualification and training; documentation of traceability through Fairchild's operation; and Fairchild verification information. Except for exigent circumstances, such requests shall not be made more than twice per year for a given category -22- of information. 14.0 PRODUCT ENGINEERING SUPPORT 14.1 The Parties will cooperate in allowing National employees to have reasonable access to the Facilities during the term of this Agreement (the "National Engineering Team"), in order to assist in Product developments and improvements. Fairchild will provide reasonable office space to the National Engineering Team, if required on a temporary basis not to exceed sixty (60) days per occurrence, at no expense to National. Should the National Engineering Team require long term, dedicated office space, National agrees to pay Fairchild the overhead cost associated with such space. The National Engineering Team will comply with all applicable Fairchild regulations in force at the Facilities and National hereby agrees to hold Fairchild harmless for any damages or liability caused by any member of the National Engineering Team, which are attributable to: (i) the negligence or willful malfeasance of such member, and (ii) any failure by such member to comply with Fairchild's regulations in force at the Facilities or with applicable law. 14.2 Fairchild shall assist the efforts of the National Engineering Team and provide National with reasonable and timely support. 14.3 Fairchild shall assist National in any efforts to identify any reliability problems that may arise in a Product. National shall correct Product related problems and Fairchild shall correct all Process related problems. 15.0 TERM AND TERMINATION 15.1 The term of this Agreement shall be thirty-nine (39) fiscal periods from the Effective Date; provided, however, that the Parties shall not less than eight (8) fiscal periods prior to the end of such thirty-ninth (39th) fiscal period determine in good faith either an extension to this Agreement or a ramp-down schedule of production so as to minimize disruption to both Parties. If the Parties are unable to agree on the terms governing a ramp-down, National shall be allowed to reduce -23- its purchase commitment by not more than twenty percent (20%) per fiscal quarter, starting one fiscal quarter after the initial thirty-nine (39) fiscal period term of this Agreement. National will provide Fairchild with not less than ninety (90) days prior written notice of any such reduction. 15.2 This Agreement may be terminated, in whole or in part, by one Party sending a written notice to the other Party of the termination of this Agreement, which notice specifies the reason for the termination, upon the happening of any one or more of the following events: (a) the other Party is the subject of a petition filed in a bankruptcy court of competent jurisdiction, whether voluntary or involuntary, which petition in the event of an involuntary petition is not dismissed within sixty (60) days; if a receiver or trustee is appointed for all or a substantial portion of the assets of the other Party; or if the other Party makes an assignment for the benefit of its creditors; or (b) the other Party fails to perform substantially any material covenant or obligation, or breaches any material representation or warranty provided for herein; provided, however, that no right of termination shall arise hereunder until sixty (60) days after receipt of written notice by the Party who has failed to perform from the other Party, specifying the failure of performance, and said failure having not been remedied or cured during said sixty (60) day period. 15.3 Upon termination of this Agreement, all rights granted hereunder shall immediately terminate and each Party shall return to the other Party any property belonging to the other Party which is in its possession, except that Fairchild may continue to retain and use any rights or property belonging to National solely for the period necessary for it to finish manufacturing the currently forecasted Fairchild Assured Capacity and/or complete any production ramp-down activity. Nothing in this Section 15 is intended to relieve either Party of any liability for any payment or other obligations -24- existing at the time of termination. 15.4 The provisions of Sections 2, 12, 16, 17 and Paragraphs 19.5 and 19.8 shall survive the termination of this Agreement for any reason. 16.0 EXPORT CONTROL 16.1 The Parties acknowledge that each must comply with all rules and laws of the United States government relating to restrictions on export. Each Party agrees to use its Best Efforts to obtain any export licenses, letters of assurance or other documents necessary with respect to this Agreement. 16.2 Each Party agrees to comply fully with United States export laws and regulations, assuring the other Party that, unless prior authorization is obtained from the competent United States government agency, the receiving Party does not intend and shall not knowingly export or re-export, directly or indirectly, any Wafers, Products, technology or technical information received hereunder, that would be in contravention of any laws and regulations published by any United States government agency. 17.0 CONFIDENTIALITY 17.1 For purposes of this Agreement, "Confidential Information" shall mean all proprietary information, including National and/or Fairchild trade secrets relating to the subject matter of this Agreement disclosed by one of the Parties to the other Party in written and/or graphic form and originally designated in writing by the disclosing Party as Confidential Information or by words of similar import, or, if disclosed orally, summarized and confirmed in writing by the disclosing Party within thirty (30) days after said oral disclosure, that the orally disclosed information is Confidential Information. 17.2 Except as may otherwise be provided in the Technology Licensing and Transfer Agreement, each Party agrees that it will not use in any way for its own account, or for the account of any third party, nor disclose to any third party except pursuant to this -25- Agreement, any Confidential Information revealed to it by the other Party. Each Party shall take every reasonable precaution to protect the confidentiality of said information. Each Party shall use the same standard of care in protecting the Confidential Information of the other Party as it normally uses in protecting its own trade secrets and proprietary information. 17.3 Notwithstanding any other provision of this Agreement, no information received by a Party hereunder shall be Confidential Information if said information is or becomes: (a) published or otherwise made available to the public other than by a breach of this Agreement; (b) furnished to a Party by a third party without restriction on its dissemination; (c) approved for release in writing by the Party designating said information as Confidential Information; (d) known to, or independently developed by, the Party receiving Confidential Information hereunder without reference to or use of said Confidential Information; or (e) disclosed to a third party by the Party transferring said information hereunder without restricting its subsequent disclosure and use by said third party. 17.4 In the event that either Party determines on the advice of its counsel that it is required to disclose any information pursuant to applicable law or receives any demand under lawful process to disclose or provide information of the other Party that is subject to the confidentiality provisions hereof, such Party shall notify the other Party prior to disclosing and providing such information and shall cooperate at the expense of the requesting Party in seeking any reasonable protective arrangements requested by such other Party. Subject to the foregoing, the Party that receives such request may thereafter disclose or provide information to the extent required by such law (as so advised by counsel) or by lawful -26- process. 18.0 REPORTS AND COMMUNICATIONS 18.1 Each Party hereby appoints a Program Manager whose responsibilities shall include acting as a focal point for the technical and commercial discussions between them related to the subject matter of this Agreement, to include monitoring within his or her respective company the distribution of Confidential Information received from the other Party and assisting in the prevention of the unauthorized disclosure of Confidential Information within the company and to third parties. The Program Managers shall also be responsible for maintaining pertinent records and arranging such conferences, visits, reports and other communications as are necessary to fulfill the terms and conditions of this Agreement. The names, addresses and telephone numbers of the Program Managers will be communicated between the Parties from time to time. 19.0 GENERAL 19.1 AMENDMENT: This Agreement may be modified only by a written document signed by duly authorized representatives of the Parties. 19.2 FORCE MAJEURE: A Party shall not be liable for a failure or delay in the performance of any of its obligations under this Agreement where such failure or delay is the result of fire, flood, or other natural disaster, act of God, war, embargo, riot, labor dispute, unavailability of raw materials or utilities (provided that such unavailability is not caused by the actions or inactions of the Party claiming force majeure), or the intervention of any government authority, providing that the Party failing in or delaying its performance immediately notifies the other Party of its inability to perform and states the reason for such inability. 19.3 ASSIGNMENT: This Agreement may not be assigned by any Party hereto without the written consent of the other Party; provided that Fairchild may assign its rights but not its obligations hereunder as collateral security to any bona fide financial institution engaged in acquisition financing in the -27- ordinary course providing financing to consummate the transactions contemplated by the Purchase Agreement or any bona fide financial institution engaged in acquisition financing in the ordinary course through whom such financing is refunded, replaced, or refinanced and any of the foregoing financial institutions may assign such rights in connection with a sale of Fairchild or the Business in the form then being conducted by Fairchild substantially as an entirety. Subject to the foregoing, all of the terms and provisions of this Agreement shall be binding upon, and inure to the benefit of, and shall be enforceable by, the respective successors and assigns of the Parties hereto. 19.4 COUNTERPARTS: This Agreement may be executed simultaneously in two or more counterparts, each of which shall be deemed an original and all of which together shall constitute but one and the same instrument. 19.5 CHOICE OF LAW: This Agreement, and the rights and obligations of the Parties hereto, shall be interpreted and governed in accordance with the laws of the State of California, without giving effect to its conflicts of law provisions. 19.6 WAIVER: Should either of the Parties fail to exercise or enforce any provision of this Agreement such failure shall not be construed as constituting a waiver or a continuing waiver of its rights to enforce such provision or right or any other provision or right. Should either of the Parties waive any provision or right under this Agreement, such waiver shall not be construed as constituting a waiver of any other provision or right. 19.7 SEVERABILITY: If any provision of this Agreement or the application thereof to any situation or circumstance shall be invalid or unenforceable, the remainder of this Agreement shall not be affected, and each remaining provision shall be valid and enforceable to the fullest extent. 19.8 LIMITATION OF LIABILITY: IN NO EVENT SHALL EITHER PARTY BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM THE OTHER PARTY'S PERFORMANCE OR FAILURE TO PERFORM UNDER THIS AGREEMENT, OR THE FURNISHING, PERFORMANCE, OR USE OF ANY GOODS OR SERVICES SOLD PURSUANT HERE- -28- TO, WHETHER DUE TO BREACH OF CONTRACT, BREACH OF WARRANTY, NEGLIGENCE OR OTHERWISE, REGARDLESS OF WHETHER THE NONPERFORMING PARTY WAS ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR NOT. 19.9 EFFECT OF HEADINGS: The headings and sub-headings contained herein are for information purposes only and shall have no effect upon the intended purpose or interpretation of the provisions of this Agreement. 19.10 INTEGRATION: The agreement of the Parties, which is composed of this Agreement and the Exhibits hereto and the documents referred to herein, constitutes the entire agreement and understanding between the Parties with respect to the subject matter of this Agreement and integrates all prior discussions and proposals (whether oral or written) between them related to the subject matter hereof. 19.11 PUBLIC ANNOUNCEMENT: Prior to the closing of the transactions contemplated under the Purchase Agreement, neither Fairchild nor National shall, without the approval of the other Party hereto, make any press release or other public announcement concerning the terms of the transactions contemplated by this Agreement, except as and to the extent that any such Party shall be so obligated by law, in which case the Party shall use its Best Efforts to advise the other Party thereof and the Parties shall use their Best Efforts to cause a mutually agreeable release or announcement to be issued; provided that the foregoing shall not preclude communications or disclosures necessary to (a) implement the provisions of this Agreement or (b) comply with accounting, securities laws and Securities and Exchange Commission disclosure obligations. Fairchild shall provide National with a reasonable opportunity to review and comment on any references to National made by Fairchild (and shall not include any such references to National without the written consent of National, which consent shall not be unreasonably withheld or delayed) in any written materials that are intended to be filed with the Securities and Exchange Commission in connection with obtaining financing required to effect the transactions contemplated in connection with the Purchase Agreement or intended to be distributed to prospective purchasers pursuant to an offering made under Rule 144A promulgated -29- under the Securities Act of 1933 in connection with obtaining such financing. 19.12 NO PARTNERSHIP OR AGENCY CREATED: Nothing contained herein or done pursuant to this Agreement shall constitute the Parties as entering upon a joint venture or partnership, or shall constitute either Party the agent for the other Party for any purpose or in any sense whatsoever. 19.13 BINDING EFFECT: This Agreement and the rights and obligations hereunder shall be binding upon and inure to the benefit of the Parties hereto and to their respective successors and assigns. 19.14 NOTICES: All notices, requests, demands and other communications which are required or may be given under this Agreement shall be in writing and shall be deemed to have been duly given when received if personally delivered; when transmitted if transmitted by telecopy, electronic or digital transmission method; the day after it is sent, if sent for next day delivery to a domestic address by a recognized overnight delivery service (e.g. Federal Express) and upon receipt, if sent by certified or registered mail, return receipt requested. In each case notice shall be sent to: National: National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 MS 16-135 Santa Clara, CA 95052-8090 Attn: General Counsel FAX: (408) 733-0293 Fairchild: Fairchild Semiconductor Corporation MS 01-00 (General Counsel) 333 Western Avenue South Portland, ME 04106 FAX: (207) 761-6020 or to such other place as such Party may designate as to itself by written notice to the other Party. -30- IN WITNESS WHEREOF, the Parties have had this Agreement executed by their respective duly authorized officers on the day and date first written above. The persons signing warrant that they are duly authorized to sign for and on behalf of the respective parties. NATIONAL SEMICONDUCTOR CORPORATION By: /s/ John M. Clark III ---------------------------------- Title: Senior Vice President FAIRCHILD SEMICONDUCTOR CORPORATION By: /s/ Joseph R. Martin ---------------------------------- Title: Executive Vice President, CFO -31- EXHIBIT A PROCESSES 4-inch Wafer Process Flows: Fairchild Maine Fab 4100 - -------------------------------------------------------------------------------- Process Description and Process Name Acceptance Specification Status - -------------------------------------------------------------------------------- ANALOG 5(mu) Bipolar Process Prod Spec: Exhibit F - Fab 4100 "ANALOG" - -------------------------------------------------------------------------------- BUS 4(mu) Bipolar, Low Power Schottky optimized for Prod Bus Interface applications Spec: Exhibit F - Fab 4100 "BUS" - -------------------------------------------------------------------------------- CGS 4(mu) Bipolar, Low Power Schottky optimized for Prod Clock Generator applications Spec: Exhibit F - Fab 4100 "CGS" - -------------------------------------------------------------------------------- DRAM 3(mu) FAST, Bipolar Schottky optomized for DRAM Prod controller applications Spec: Exhibit F- Fab 4100 "DRAM" - -------------------------------------------------------------------------------- DTCOMM 3(mu) FAST, Bipolar Schottky optimized for data Prod communications applications Spec: Exhibit F - Fab 4100 "DTCOMM" - -------------------------------------------------------------------------------- DTP 4(mu) Bipolar, Low Power Schottky Prod Spec: Exhibit F- Fab 4100 "DTP" - -------------------------------------------------------------------------------- LAN 4(mu) Bipolar, Low Power Schottky optimized for Prod LAN applications Spec: Exhibit F- Fab 4100 "LAN" - -------------------------------------------------------------------------------- PTP 4(mu) Bipolar, Low Power Schottky optimized for Prod point-to-point applications Spec: Exhibit F - Fab 4100 "PTP" - -------------------------------------------------------------------------------- PTPCMOS 4(mu) Si Gate CMOS optimized for point-to-point Prod applications Spec: Exhibit F - Fab 4100 "PTPCMOS" - -------------------------------------------------------------------------------- RTCCMOS 3(mu) Si Gate CMOS optimized for real time clock Prod applications Spec: Exhibit F - Fab 4100 "RTCCMOS" - -------------------------------------------------------------------------------- 5 inch Wafer Process Flows: Fairchild Maine Fab 5100 - -------------------------------------------------------------------------------- Process Name Process Description and Acceptance Specification Status - -------------------------------------------------------------------------------- GA20 2(mu) FACT Gate Arrays Prod Spec: Exhibit F - Fab 5100 "GA20" - -------------------------------------------------------------------------------- ALS15 1.5(mu) Bipolar, Low Power Schottky for Read Prod Channel circuits Spec: Exhibit F - Fab 5100 "ALS15" - -------------------------------------------------------------------------------- CGSP/E 2.5(mu) HCMOS Prod Spec: Exhibit F - Fab 5100 "GCSP/E" - -------------------------------------------------------------------------------- 6-inch Wafer Process Flows: Fairchild Maine Fab 6001 - -------------------------------------------------------------------------------- Process Description and Equivalency Process Name Acceptance Specification Weight Status - -------------------------------------------------------------------------------- ABIC2L ABiC-4 with two layers of metal, with a 1.65 Dev mid-flow inventory point for subsequent 06 ASIC personalization. 0.8u BiCMOS Spec: Exhibit F - Fab 6001 "ABIC2L & ABIC2LM" - -------------------------------------------------------------------------------- ABIC2LM ABiC-4 with two layers of metal, for use 1.65 Prod in RF products. 0.8(mu) BiCMOS Spec: Exhibit F - Fab 6001 "ABIC2L & ABIC2LM" - -------------------------------------------------------------------------------- ABIC3L ABiC-4 with three layers of metal, with 1.85 Dev a mid-flow inventory point for 06 subsequent ASIC personalization. 0.8(mu) BiCMOS Spec: Exhibit F - Fab 6001 "ABIC3L & ABIC4L" - -------------------------------------------------------------------------------- ABIC4L ABiC-4 with four layers of metal, with a 2.00 Dev mid-flow inventory point for subsequent 06 ASIC personalization. 0.8(mu) BiCMOS Spec: Exhibit F - Fab 6001 "ABIC3L & ABIC4L" - -------------------------------------------------------------------------------- ABIC52L ABiC-5 with two layers of metal and 1.65 Dev 0.5(mu), three sided emitter, for use in 06 RF products. CMOS remains at 0.8(mu) Spec: Exhibit F - Fab 6001 "ABIC52L" - -------------------------------------------------------------------------------- -2- - -------------------------------------------------------------------------------- BUS 1.0(mu) BiCMOS (1.0BCT) 1.5 Prod Spec: Exhibit F - Fab 6001 "BUSA & CGS10" - -------------------------------------------------------------------------------- CS080C 0.8(mu) Core CMOS, with two layers of 1.0 Prod metal and W-plug contact structure. Spec: Exhibit F - Fab 6001 "CS080C" - -------------------------------------------------------------------------------- CS080CB1 BiCMOS version of CS080, with two layers 1.45 Prod of metal and isolated NMOS devices Spec: Exhibit F - Fab 6001 "CS080CB1" - -------------------------------------------------------------------------------- CS080CBTX BiCMOS version of CS080, with two layers 1.27 Prod of metal and conventional epi, emulating CS080AB run in Texas Spec: Exhibit F - Fab 6001 "CS080CBTX" - -------------------------------------------------------------------------------- CS080CBIHY BiCMOS version of CS080, with two layers 1.45 Dev of metal, isolated NMOS devices, high 06 voltage NPN and Schottky diode Spec: Exhibit F - Fab 6001 "CS080CBIHY" - -------------------------------------------------------------------------------- CS080CBIP BiCMOS version of CS080, with two layers 1.45 Dev of metal, isolated NMOS devices and 06 double poly capacitor Spec: Exhibit F - Fab 6001 "CS080CBIP" - -------------------------------------------------------------------------------- CS080CBIVU BiCMOS version of CS080, with two layers 1.45 Dev of metal isolated NMOS devices and 04 vertical PNP device Spec: Exhibit F - Fab 6001 "CS080CBIVU" - -------------------------------------------------------------------------------- CGS10 1.0(mu) BiCMOS (1.0BCT) 1.5 Prod Spec: Exhibit F - Fab 6001 "BUS & CGS10" - -------------------------------------------------------------------------------- -3- 6-inch Wafer Process Flows: Fairchild Utah Fab 3 - -------------------------------------------------------------------- Process Name Process Description and Acceptance Specification Status - -------------------------------------------------------------------- CE80SLM 0.8(mu) EPROM process with one layer of Prod metal and AMG style cells Spec: SOP-3060, TS-3020, TS-3021 (Salt Lake) - -------------------------------------------------------------------- CE080DLM 0.8(mu) EPROM process with two layers of Prod metal and AMG style cells Spec: SOP-3060, TS-3020, TS-3021 (Salt Lake) - -------------------------------------------------------------------- CS100P 1.0(mu) Core CMOS process, with Prod poly-to-poly capacitor and two layers of metal Spec: SOP-3060, TS-3020, TS-3021 (Salt Lake) - -------------------------------------------------------------------- CS100HE2 Dense EEPROM variation of CS100, with Prod double poly and double metal Spec: SOP-3060, TS-3020, TS-3021 (Salt Lake) - -------------------------------------------------------------------- CS80SG Low density EEPROM variation of CS080 Dev 07 with double poly and double metal Spec: SOP-3060, TS-3020, TS-3021 (Salt Lake) - -------------------------------------------------------------------- CS80SG3 Low density EEPROM variation of CS080 Dev 06 with double poly and triple metal Spec: SOP-3060, TS-3020, TS-3021 (Salt Lake) - -------------------------------------------------------------------- CS065SE Dense EEPROM variation of CS065S, with Dev 05 double poly and double metal Spec: SOP-3060, TS-3020, TS-3021 (Salt Lake) - -------------------------------------------------------------------- The following process flows are being discontinued, and no long term manufacturing commitment can be supported. - -------------------------------------------------------------------- Process Description and Process Name Acceptance Specification Status - -------------------------------------------------------------------- CE130 1.2(mu) EPROM process with one layer of Obsolete metal and "Split Gate" style cells on Spec: SOP-3060, TS-3020, TS-3021 (Salt 4/20/97 Lake) - -------------------------------------------------------------------- -4- Exhibit B Product List and Supporting Data Products manufactured in West Jordan, Utah - ------------------------------------------------------------------------------------------------------------------------------- Division Business AFM Product ID PDI Code Process Flow Sort Test Sort MYA Baseline Die Cost Share Unit Wafer/Hour Yield - ------------------------------------------------------------------------------------------------------------------------------- Analog DAP A7 ADC12062 ADC1206BZ6 CS100HE2 N/A N/A 48% 80% Analog Mil 1T KSD64 KSD64A CS100HE2 N/A N/A N/A N/A Analog DAP A5 LM75 LM75A CS100HE2 Versatest V210 N/A 51% 85% Yes Analog DAP AT LM78 LM78A CS100HE2 N/A 0.88 45% 75% Analog POWER 6J LM3810 LM3810A CS100HE2 N/A N/A N/A N/A Analog FPD G2 LMC8310 LMC8310A CS100HE2 N/A N/A N/A N/A Analog AMPS G2 LMC6953 LMC6953A CS100HE2 N/A N/A 50% 84% Analog AMPS 6J LMC6980 LMC6980A CS080SG N/A N/A N/A N/A Analog POWER 6J LM3621A LM3621A CS100HE2 N/A N/A N/A N/A Analog POWER 6J LM3641 LM3641B CS100HE2 N/A N/A N/A N/A Analog POWER 2U LP3470 LP3470AZ CS100HE2 N/A N/A N/A N/A PSD MICRO 2U COP7C256 COP7C256B CE80SLM Versatest V2 0.4 44% 73% Yes PSD MICRO 2U COP7C257 COP7C257B CE80SLM Versatest V2 0.4 44% 73% Yes PSD MICRO 2U COP8780 COP8780C CE130 Versatest V2 N/A 47% 79% PSD MICRO 2U NMC8C64 NMC8C64A CE130 Versatest V2 1.5 52% 87% Yes PSD MICRO 2U COP87SAC COP87SACA CE80DLM Versatest V2 0.6 51% 81% Yes PSD MICRO 2U COP8SAA7 COP8SAA7A CE80DLM Versatest V2 0.3 53% 85% PSD MICRO 2U CR16AHT7 CR16AHT7A CE80DLM Versatest V2 0.8 20% 33% PSD MICRO 2U CR16MHR5 CR16MHR5A CS065SE Versatest V2 0.8 N/A N/A PSD MICRO 2U CR16MHR6 CR16MHR6A CS065SE Versatest V2 2.4 N/A N/A All devices which show N/A for sort are sorted eithr in Santa Calra or Malacca (NSC) Exhibit B Product List and Supporting Data Products manufactured in Arlington, Texas - ------------------------------------------------------------------------------------------------------------------------------ Division Business AFM Product ID PDI Code Process Flow Sort Test Sort MYA Baseline Die Cost Unit Wafer/Hour Yield Share - ------------------------------------------------------------------------------------------------------------------------------ Memory E2PROM 84 NMC24C16A CS160/EE Megatest Q2/52 1.50 55% 92% Memory E2PROM 84 NMC25C14A CS160/EE Megatest Q2/52 0.35 55% 92% Memory E2PROM 84 NMC59C16A CS160/EE Megatest Q2/52 1.00 55% 92% Memory E2PROM 84 NMC66C02A CS160/EE Megatest Q2/52 1.50 55% 92% Yes Memory E2PROM 84 NMC66C04A CS160/EE Megatest Q2/52 0.67 55% 92% Memory E2PROM 84 NMC66C06A CS160/EE Megatest Q2/52 1.00 55% 92% Memory E2PROM 84 NMC66C08A CS160/EE Megatest Q2/52 0.75 55% 92% Memory E2PROM 84 NMC66C16A CS160/EE Megatest Q2/52 1.50 55% 92% Memory E2PROM 84 NMC66C46A CS160/EE Megatest Q2/52 1.00 55% 92% Memory E2PROM 84 NMC66C47A CS160/EE Megatest Q2/52 0.92 55% 92% Yes Memory E2PROM 84 NMC66C56A CS160/EE Megatest Q2/52 1.33 55% 92% Yes Memory E2PROM 84 NMC66C57A CS160/EE Megatest Q2/52 1.00 55% 92% Memory E2PROM 84 NMC66C66A CS160/EE Megatest Q2/52 1.00 55% 92% Memory E2PROM 84 NMC88C06A CS160/EE Megatest Q2/52 1.00 55% 92% Memory E2PROM 84 NMC88C11A CS200B/EE Megatest Q2/52 0.67 55% 92% Memory E2PROM 84 NMC88C46A CS160/EE Megatest Q2/52 1.00 55% 92% Memory E2PROM 84 NMC88C47A CS160/EE Megatest Q2/52 0.92 55% 92% Memory E2PROM 84 NMC93C06A CS160/EE Megatest Q2/52 1.00 55% 92% Memory E2PROM 84 NMC93C07B CS160/EE Megatest Q2/52 1.00 55% 92% Memory E2PROM 84 NMC93C11A CS160/EE Megatest Q2/52 0.67 55% 92% Memory E2PROM 84 NMC93C46C CS160/EE Megatest Q2/52 1.00 55% 92% Yes Memory E2PROM 84 NMC93C47A CS200B/EE Megatest Q2/52 0.92 55% 92% Memory E2PROM 84 NMC93C55A CS200B/EE Megatest Q2/52 1.20 55% 92% Memory E2PROM 84 NMC93C56B CS200B/EE Megatest Q2/52 1.33 55% 92% Memory E2PROM 84 NMC93C57C CS200B/EE Megatest Q2/52 0.40 55% 92% Memory E2PROM 84 NMC93C66A CS200B/EE Megatest Q2/52 1.00 55% 92% Memory E2PROM 84 NMC95C12A CS160/EE Megatest Q2/52 0.33 55% 92% Memory E2PROM 84 NMC93C12C CS160/EE Megatest Q2/52 0.33 55% 92% Logic CMOS W1 GTLP16612B6B CS080A Megatest Q2/52 Non-sort 55% 92% Exhibit B Product List and Supporting Data - ------------------------------------------------------------------------------------------------------------------------------------ Division Business Unit AFM Product ID PDI Code Process Sort Test Sort MYA Baseline Die Cost Flow Wafer/Hour Yield Share - ------------------------------------------------------------------------------------------------------------------------------------ ANALOG COMLINEAR R3 307010A6B 307010A6B-BAA ABIC2LM NATIONAL N/A N/A N/A ANALOG COMLINEAR R3 397012A6B 397012A6B-BAA ABIC2LM NATIONAL N/A N/A N/A ANALOG COMLINEAR R4 397013B6B 397013B6B-BBA ABIC2LM NATIONAL N/A N/A N/A ANALOG COMLINEAR R4 397013B6B 397013B6B-BCA ABIC2LM NATIONAL N/A N/A N/A ANALOG COMLINEAR R4 387017A6B 387017A6B-BAA ABIC2LM NATIONAL N/A N/A N/A ANALOG INTERFACE BUS 4K DM8640A4B DM8640A4B-TAB BUS MCT20XX 2.4 50% 83% CIRCUIT ANALOG INTERFACE BUS 4K DM8641A4B DM86414B-TAB BUS MCT20XX 2.4 53% 89% CIRCUIT ANALOG INTERFACE BUS 4K DM8833B4B DM8833B4B-TAB BUS MCT20XX 2.4 N/A N/A CIRCUIT ANALOG INTERFACE BUS 4K DM8834B4B DM8834B4B-TAB BUS MCT20XX 2.4 N/A N/A CIRCUIT ANALOG INTERFACE BUS 4K DM8835B4B DM8835B4B-TAB BUS MCT20XX 2.4 N/A N/A CIRCUIT ANALOG INTERFACE BUS 4K DM8836B4B DM8836B4B-TAB BUS MCT20XX 2.4 50% 83% CIRCUIT ANALOG INTERFACE BUS 4K DM8837B4B DM8837B4B-TAB BUS MCT20XX 2.4 50% 83% CIRCUIT ANALOG INTERFACE BUS 4K DM8838A4B DM8838A4B-TAB BUS MCT20XX 2.4 58% 96% CIRCUIT ANALOG INTERFACE BUS 4K DM8839B4B DM8839B4B-TAB BUS MCT20XX 2.4 N/A N/A CIRCUIT ANALOG INTERFACE BUS 4K DP7303C4B DP7303C4B-TAA BUS MCT20XX 2.4 58% 96% CIRCUIT ANALOG INTERFACE BUS 4K DP7304C4B DP7304C4B-TAA BUS MCT20XX 2.4 52% 86% CIRCUIT ANALOG INTERFACE BUS 4K DP7307C4B DP7307C4B-TAA BUS MCT20XX 2.4 50% 83% CIRCUIT ANALOG INTERFACE BUS 4K DP7308C4B DP7308C4B-TAA BUS MCT20XX 2.4 N/A N/A CIRCUIT ANALOG INTERFACE BUS 4K DS1662C4B DS1662C4B-TAA BUS MCT20XX 2.4 53% 88% CIRCUIT ANALOG INTERFACE BUS 4K DS1667C4B DS1667C4B-TAA BUS MCT20XX 2.4 N/A N/A CIRCUIT ANALOG INTERFACE BUS 4K DS1776Z4B DS1776Z4B-TAA BUS MCT20XX 2.4 N/A N/A CIRCUIT ANALOG INTERFACE BUS 4K DS1772Z4B DS1777Z4B-TAA BUS MCT20XX 2.4 N/A N/A CIRCUIT ANALOG INTERFACE BUS 4K DS55160C4B DS55160C4B-TAA BUS MCT20XX 2.4 55% 91% CIRCUIT ANALOG INTERFACE BUS 4K DS55161C4B DS55161C4B-TAA BUS MCT20XX 2.4 53% 88% CIRCUIT ANALOG INTERFACE BUS 4K DS55162C4B DS55162C4B-TAA BUS MCT20XX 2.4 53% 88% CIRCUIT ANALOG INTERFACE BUS 4K DS76S10A4B DS76S10A4B-TAA BUS MCT20XX 2.4 58% 96% CIRCUIT ANALOG INTERFACE BUS 4K DS76S11A4B DS76S11A4B-TAA BUS MCT20XX 2.4 N/A N/A CIRCUIT ANALOG INTERFACE BUS 4K T3883B6B T3883B6B-BAB BUS BCT1.0 MCT20XX 1.9 N/A N/A CIRCUIT ANALOG INTERFACE BUS 4K T3884B6B T3884B6B-BGA BUS BCT1.0 MCT20XX 1.9 51% 85% CIRCUIT ANALOG INTERFACE BUS 4K T3886B6B T3886B6B-BLA BUS BCT1.0 MCT20XX 1.9 52% 86% CIRCUIT ANALOG INTERFACE DATACOM H1 DS1691A4B DS1619A4B-TAA DTCOMM MCT20XX 2.4 55% 91% ANALOG INTERFACE DATACOM H1 DS26LS31B4B DS26LS31B4B-TAA DTCOMM MCT20XX 2.4 55% 96% YES ANALOG INTERFACE DATACOM H1 DS26LS31B4B DS26LS31B4B-TAA/E DTCOMM MCT20XX 2.4 55% 92% ANALOG INTERFACE DATACOM H1 DS26LS32B4B DS26LS32B4B-TAA DTCOMM MCT20XX 2.4 56% 93% YES ANALOG INTERFACE DATACOM H1 DS26LS32B4B DS26LS32B4B-TAA/E DTCOMM MCT20XX 2.4 N/A N/A ANALOG INTERFACE DATACOM H1 DS26LS33B4B DS26LS33B4B-TAA DTCOMM MCT20XX 2.4 55% 92% YES ANALOG INTERFACE DATACOM H1 DS347B4B DS3487B4B-TAA DTCOMM MCT20XX 2.0 56% 94% YES ANALOG INTERFACE DATACOM H1 DS3586A4B DS3586A4B-TAA DTCOMM MCT20XX 2.0 58% 96% YES ANALOG INTERFACE DATACOM H1 DS3587B4B DS3587B4B-TAA DTCOMM MCT20XX 2.0 N/A N/A ANALOG INTERFACE DATACOM H1 DS7632A4B DS7632A4B-TAA DTCOMM MCT20XX 1.2 57% 95% ANALOG INTERFACE DATACOM H1 DS7632A4B DS7632A4B-TAA/E DTCOMM MCT20XX 1.2 55% 92% ANALOG INTERFACE DATACOM H1 DS7633A4B DS7633A4B-TAA DTCOMM MCT20XX 1.2 55% 92% ANALOG INTERFACE DATACOM H1 DS78C120A4B DS78C120A4B-TAA DTCOMM MCT20XX 2.0 55% 92% ANALOG INTERFACE DATACOM H1 DS78C120A4B DS78C120A4B-TAA/E DTCOMM MCT20XX 2.0 N/A N/A ANALOG INTERFACE DATACOM H1 DS78LS120A4B DS78LS120A4B-TAA DTCOMM MCT20XX 2.0 N/A N/A ANALOG INTERFACE DATACOM H1 DS78LS120A4B DS78LS120A4B-TAA/E DTCOMM MCT20XX 2.0 N/A N/A - ------------------------------------------------------------------------------------------------------------------------------------ Division Business Unit AFM Product ID PDI Code Process Sort Test Sort MYA Baseline Die Cost Flow Wafer/Hour Yield Share - ------------------------------------------------------------------------------------------------------------------------------------ ANALOG INTERFACE DATACOM H1 DS8921A4B DS8921A4B-TAA DTCOMM MCT20XX 2.4 56% 94% ANALOG INTERFACE DATACOM H1 DS8922A4B DS89922A4B-TAA DTCOMM MCT20XX 2.4 54% 90% ANALOG INTERFACE DATACOM H1 DS8923A4B DS8923A4B-TAA DTCOMM MCT20XX 2.4 55% 92% ANALOG INTERFACE DATACOM H1 DS8925B4B DS8925B4B-TBA DTCOMM MCT20XX 2.4 53% 89% ANALOG INTERFACE DATACOM H1 DS8926A4B DS8926A4B-TAA-PQ DTCOMM MCT20XX 2.4 N/A N/A ANALOG INTERFACE DATACOM H1 DS8933A4B DS8933A4B-TAA DTCOMM MCT20XX 2.4 54% 90% ANALOG INTERFACE DATACOM H1 DS8934A4B DS8934A4B-TAA DTCOMM MCT20XX 2.4 50% 84% ANALOG INTERFACE DATACOM H1 DS8935A4B DS8935A4B-TAA DTCOMM MCT20XX 2.4 N/A N/A ANALOG INTERFACE DATACOM H1 DS8936A4B DS8936A4B-TAA-PQ DTCOMM MCT20XX 2.4 N/A N/A ANALOG INTERFACE DATACOM H1 9636A4B 9636A4B-TAA DTCOMM MCT20XX 2.2 55% 92% ANALOG INTERFACE DATACOM H1 9637A4B 9637A4B-TBA DTCOMM MCT20XX 2.2 57% 95% ANALOG INTERFACE DATACOM H1 9638A4B 9638A4B-TDB DTCOMM MCT20XX 2.2 55% 92% ANALOG INTERFACE DATACOM H1 9638A4B 9638A4B-TDB/E DTCOMM MCT20XX 2.2 N/A N/A ANALOG INTERFACE DATACOM H1 9639A4B 9639A4B-TAA DTCOMM MCT20XX 2.2 57% 95% Exhibit B Product List and Supporting Data - ------------------------------------------------------------------------------------------------------------------------------------ Division Business Unit AFM Product ID PDI Code Process Flow Sort Test Sort MYA Baseline Die Cost Wafer/Hour Yield Share - ------------------------------------------------------------------------------------------------------------------------------------ ANALOG INTERFACE MULTIPOINT 80 DM8830E4B DM8830E4B-TAB DTP MCT20XX 2.1 55% 92% ANALOG INTERFACE MULTIPOINT 80 DM8830E4B DM8830E4B-TAB/D DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 DM8831B4B DM8831B4B-TAB DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 DM8832B4B DM8832B4B-TAB DTP MCT20XX 2.1 53% 89% ANALOG INTERFACE MULTIPOINT 80 DM8832B4B DM8832B4B-TAB/E DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 DS16195C4B DS16195C4B-TBA DTP MCT20XX 2.1 56% 93% YES ANALOG INTERFACE MULTIPOINT 80 DS16196B4B DS16196B4B-TAA DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 DS16196C4B DS16196C4B-TAA DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 DS1650A4B DS1650A4B-TAA DTP MCT20XX 2.1 57% 95% ANALOG INTERFACE MULTIPOINT 80 DS1652A4B DS16542A4B-TAA DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 DS1695A4B DS1695A4B-TBA DTP MCT20XX 2.1 55% 92% YES ANALOG INTERFACE MULTIPOINT 80 DS1696A4B DS1696A4B-TAA DTP MCT20XX 2.1 56% 94% ANALOG INTERFACE MULTIPOINT 80 DS1697A4B DS1697A4B-TAA DTP MCT20XX 2.1 58% 97% ANALOG INTERFACE MULTIPOINT 80 DS1698A4B DS1698A4B-TAA DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 DS36276C4B DS36276C4B-TAA DTP MCT20XX 2.1 41% 69% ANALOG INTERFACE MULTIPOINT 80 DS36277C4B DS36277C4B-TAA DTP MCT20XX 2.1 54% 90% YES ANALOG INTERFACE MULTIPOINT 80 DS3695A4B DS3695A4B-TAA DTP MCT20XX 2.1 55% 92% ANALOG INTERFACE MULTIPOINT 80 DS75113A4B DS75113A4B-TAB DTP MCT20XX 2.1 55% 92% ANALOG INTERFACE MULTIPOINT 80 DS75114A4B DS75114A4B-TAB DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 DS75114A4B DS75114A4B-TAB/C DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 DS75115A4B DS75115A4B-TAB DTP MCT20XX 2.1 55% 92% ANALOG INTERFACE MULTIPOINT 80 DS75176B4B DS75175B4B-TCA DTP MCT20XX 2.1 54% 90% YES ANALOG INTERFACE MULTIPOINT 80 DS8820H4B DS8820H4B-TBB DTP MCT20XX 2.1 54% 90% ANALOG INTERFACE MULTIPOINT 80 DS8820H4B DS8820H4B-TBB/E DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 LM163A4B LM163A4B-TAB DTP MCT20XX 2.1 32% 54% ANALOG INTERFACE MULTIPOINT 80 LM3623A4B LM3623A4B-TAB DTP MCT20XX 2.1 55% 92% ANALOG INTERFACE MULTIPOINT 80 LM3624A4B LM3624A4B-TAB DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 LM75107A4B LM75107A4B-TAB DTP MCT20XX 2.1 58% 97% YES ANALOG INTERFACE MULTIPOINT 80 LM75108A4B LM75108A4B-TAB DTP MCT20XX 2.1 53% 88% ANALOG INTERFACE MULTIPOINT 80 LM75122A4B LM75122A4B-TAB DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 LM75124A4B LM75124A4B-TAB DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 X172B4B X172B4B-TCB DTP MCT20XX 3.0 35% 58% ANALOG INTERFACE MULTIPOINT 80 X173A4B X173A4B-TBB DTP MCT20XX 3.0 35% 58% YES ANALOG INTERFACE MULTIPOINT 80 X174B4B X174B4B-TCB DTP MCT20XX 3.0 N/A N/A ANALOG INTERFACE MULTIPOINT 80 X175A4B X175A4B-TBB DTP MCT20XX 3.0 35% 58% ANALOG INTERFACE MULTIPOINT 80 X176A4B X176A4B-TBB DTP MCT20XX 3.0 N/A N/A ANALOG INTERFACE MULTIPOINT 80 X177A4B X177A4B-TBB DTP MCT20XX 3.0 35% 58% ANALOG INTERFACE MULTIPOINT 80 Y107A4B Y107A4B-TBA DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 Y107A4B Y107A4B-TBA/C DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 Y110A4B Y110A4B-TBA DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 9614A4B 9614A4B-TBA DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 9614A4B 9614A4B-TBA/C DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 9614A4B 9614A4B-TBA/E DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 9615A4B 9615A4B-TBA DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 9615A4B 9615A4B-TBA/C DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 9615A4B 9615A4B-TBA/E DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 9622A4B 9622A4B-TBA DTP MCT20XX 2.1 N/A N/A ANALOG INTERFACE MULTIPOINT 80 9627A4B 9627A4B-TCA DTP MCT20XX 2.1 N/A N/A - ------------------------------------------------------------------------------------------------------------------------------------ Division Business Unit AFM Product ID PDI Code Process Flow Sort Test Sort MYA Baseline Die Cost Wafer/Hour Yield Share - ------------------------------------------------------------------------------------------------------------------------------------ ANALOG INTERFACE PT TO PT H2 DS14C202A6B DS14C202A6B-BCA-PQ CS080CBIHY MCT20XX 2.1 N/A N/A ANALOG INTERFACE PT TO PT H2 DS14C211A6B DS14C211A6B-BAA CS080CBIHY MCT20XX 2.1 N/A N/A ANALOG INTERFACE PT TO PT H2 DS14C89C4B DS14C89C4B-TCA PTPCMOS MCT20XX 2.1 54% 90% YES ANALOG INTERFACE PT TO PT H2 DS14185A4B DS14185A4B-TCA PTP MCT20XX 3.0 57% 95% YES ANALOG INTERFACE PT TO PT H2 DS14196A4B DS14169A4B-TAA PTP MCT20XX 2.1 57% 95% YES ANALOG INTERFACE PT TO PT H2 DS75150A4B DS75150A4B-TBB PTP MCT20XX 2.1 58% 96% ANALOG INTERFACE PT TO PT H2 DS75154A4B DS75154A4B-TBB PTP MCT20XX 2.1 58% 96% ANALOG INTERFACE PT TO PT H2 DS8933A4B DS8933A4B-TAA PTP MCT20XX 2.1 50% 84% ANALOG INTERFACE PT TO PT H2 DS8934B4B DS8934B4B-TBA PTP MCT20XX 2.1 52% 87% ANALOG INTERFACE PT TO PT H2 FM1488A4B FM1488A4B-TAA PTP MCT20XX 2.1 58% 96% ANALOG INTERFACE PT TO PT H2 LM1589B4B LM1589B4B-TBB PTP MCT20XX 2.1 58% 97% ANALOG INTERFACE PT TO PT H2 LM1590B4B LM1590B4B-TBB PTP MCT20XX 2.1 58% 97% ANALOG INTERFACE PT TO PT H2 9616A4B 9616A4B-TDA DTCOMM MCT20XX 2.1 N/A N/A H2 DS14C88D4B PTPCMOS 54% 90% YES Exhibit B Product List and Supporting Data - ------------------------------------------------------------------------------------------------------------------------------------ Division Business Unit AFM Product ID PDI Code Process Flow Sort Test Sort MYA Baseline Die Cost Wafer/Hour Yield Share - ------------------------------------------------------------------------------------------------------------------------------------ ANALOG WIRELESS ABIC 9W LMX150AD6B LMX1501AD6B-BAA ABIC2LM MCT20XX 0.2 30% 50% ANALOG WIRELESS ABIC 9W LMX1511D6B LMX1511D6B-BAA ABIC2LM MCT20XX 0.2 N/A N/A ANALOG WIRELESS ABIC 9W LMX2301D6B LMX2301D6B-BAA ABIC2LM MCT20XX 0.2 30% 50% ANALOG WIRELESS ABIC 9W LMX2305D6B LMX2305D6B-BAA ABIC2LM MCT20XX 0.2 30% 50% ANALOG WIRELESS ABIC 9W LMX2306B6B LMX2306B6B-BAA ABIC2LM MCT20XX 0.2 N/A N/A ANALOG WIRELESS ABIC 9W LMX2315D6B LMX2315D6B-BAA ABIC2LM MCT20XX 0.2 43% 71% YES ANALOG WIRELESS ABIC 9W LMX2316B5B LMX2316B6B-BAA ABIC2LM MCT20XX 0.2 N/A N/A ANALOG WIRELESS ABIC 9W LMX2320D6B LMX2320D6B-BAA ABIC2LM MCT20XX 0.2 46% 76% ANALOG WIRELESS ABIC 9W LMX2331B6B LMX2331C6B-BAA ABIC2LM MCT20XX 0.2 36% 60% YES ANALOG WIRELESS ABIC 9W LMX2332C6B LMX2332C6B-BAA ABIC2LM MCT20XX 0.2 34% 57% YES ANALOG WIRELESS ABIC 9W LMX2335C6B LMX2335C6B-BAA ABIC2LM MCT20XX 0.2 40% 66% YES C&C AUTO DISPLAY DRIVER 42 DM8893A4B DM8893A4B-TAB ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 DM8894A4B DM8894A4B-TAB ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 DP8310C4B DP8310C4B-TBB ANALOG MCT20XX 2.3 51% 85% C&C AUTO DISPLAY DRIVER 42 DP8311C/M4B DP8311C4/M4B-TBB ANALOG MCT20XX 2.3 53% 89% C&C AUTO DISPLAY DRIVER 42 DP8311C4B DP8311C4B-TBB ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 DS0025A4B DS0025A4B-TAB ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 DS0026B4B DS0026B4B-TBB ANALOG MCT20XX 2.3 58% 96% YES C&C AUTO DISPLAY DRIVER 42 DS0026B4B DS0026B4B-TBB/E ANALOG MCT20XX 2.3 50% 83% C&C AUTO DISPLAY DRIVER 42 DS0056B4B DS0056B4B-TAB ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 DS75325D4B DS75325D4B-TAB ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 DS75361A4B DS75361A4B-TAB ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 DS75365A4B DS75365A4B-TBB ANALOG MCT20XX 2.3 55% 92% C&C AUTO DISPLAY DRIVER 42 DS75450C4B DS75450C4B-TBB ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 DS75451B4B DS75451B4B-TAB ANALOG MCT20XX 2.3 56% 93% C&C AUTO DISPLAY DRIVER 42 DS75452B4B DS75452B4B-TAB ANALOG MCT20XX 2.3 55% 91% YES C&C AUTO DISPLAY DRIVER 42 DS75453B4B DS75453B4B-TBB ANALOG MCT20XX 2.3 56% 93% YES C&C AUTO DISPLAY DRIVER 42 DS75454B4B DS75454B4B-TBB ANALOG MCT20XX 2.3 59% 98% C&C AUTO DISPLAY DRIVER 42 DS88L12B4B DS88L12B4B-TAB ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 LM106E4B LM106E4B-TAB ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 LM1514A4B LM1514A4B-TAB ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 LM710D4B LM710D4B-TAB ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 7710A/C4G 7710A/C4G-TBA ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 7710A/M4G 7710A/M4G-TBA ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 7710A4B 7710A4B-TBA ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 7710A4G 7710A4G-TBA/C ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 7711/C4G 7711/C4G-TBA ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 7711A/C4G 7711A/C4G-TBA ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 7711A/M4G 7711A/M4G-TBA ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 7711A4G 7711A4G-TBA/C ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 9665B4B 9665B4B-TCA ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 9667B4B 9667B4B-TCA ANALOG MCT20XX 2.3 55% 92% YES C&C AUTO DISPLAY DRIVER 42 9667B4B 9667B4B-TCA/E ANALOG MCT20XX 2.3 N/A N/A C&C AUTO DISPLAY DRIVER 42 9668B4B 9668B4B-TDA ANALOG MCT20XX 2.3 56% 93% C&C CLASIC 7H CS0354B6 CS0354B6-BBAB CS80CBI UNDEFINED N/A N/A N/A N/A N/A Exhibit B Product List and Supporting Data - ------------------------------------------------------------------------------------------------------------------------------------ Division Business Unit AFM Product ID PDI Code Process Flow Sort Test Sort MYA Baseline Die Cost Wafer/Hour Yield Share - ------------------------------------------------------------------------------------------------------------------------------------ C&C LAN MEDIA 15 DP8392C4 DP8392C4-TAA LAN MCT20XX 2.1 51% 85% YES C&C LAN MEDIA 15 DP8394D4 DP8394D4-TBA LAN MCT20XX 2.1 N/A N/A C&C PLEXUS X3 DP73840B6B DP73840B6B-BBB-612 CS080CBTX LTX TRILLIU 3.3 38% 64% C&C PLEXUS X3 DP73840B6B DP73840B6B-BBB-635 CS080CBTX LTX TRILLIU 3.3 38% 64% C&C WAN ABIC 89 FNGM8902Z6B FNGM8902Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 H841Z6B H841Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 H842Z6B H842Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 H847Z6B H847Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 MB2581Z6B MB2581Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 MB8902Z6B MB8902Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 MJ2680Z6B MJ2680Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 MK2331Z6B MK2331Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 MK2518Z6B MK2518Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 MK2532Z6B MK2532Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 MK2533Z6B MK2533Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 MT2512Z6B MT2512Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 SF2669Z6B SF2669Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN ABIC 89 TS2501Z6B TS250Z6B-BAA ABIC3L/4L NATIONAL N/A N/A N/A C&C WAN GATE ARRAY 3D CA0500Y5 CA0500Y5-CAB GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CA1141Y5B CA1141Y5B-CAF GA20 SENTRY 20 2.0 42% 70% C&C WAN GATE ARRAY 3D CA1142Y5B CA1142Y5B-CAF GA20 SENTRY 20 2.0 42% 70% C&C WAN GATE ARRAY 3D CA1202Y5B CA1202Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CA1249Y5B CA1249Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CA1324Y5B CA1324Y5B-CAF GA20 SENTRY 20 2.0 42% 70% C&C WAN GATE ARRAY 3D CA1325Y5B CA1325Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CA1795Y5B CA1795Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CB1295Z5B CB1295Z5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CB1297Z5B CB1297Z5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CB1514Z5B CB1514Z5B-CAF GA20 SENTRY 20 2.0 42% 70% C&C WAN GATE ARRAY 3D CB1524Z5B CB1524Z5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CB1542Z5B CB1542Z5B-CAF GA20 SENTRY 20 2.0 42% 70% C&C WAN GATE ARRAY 3D CB1625Z5B CB1625Z5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CB1626Z5B CB1626Z5B-CAF GA20 SENTRY 20 2.0 42% 70% C&C WAN GATE ARRAY 3D CB1629Z5B CB1629Z5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CC1090Y5B CC1090Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CC1093Y5B CC1093Y5B-CAF GA20 SENTRY 20 2.0 42% 70% C&C WAN GATE ARRAY 3D CC1094Y5B CC1094Y5B-CAF GA20 SENTRY 20 2.0 42% 70% C&C WAN GATE ARRAY 3D CC1110Y5B CC1110Y5B-CAF GA20 SENTRY 20 2.0 42% 70% C&C WAN GATE ARRAY 3D CC1144Y5B CC1144Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CC150Y5B CC150Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CC1171Y5B CC171Y5B-CAF GA20 SENTRY 20 2.0 49% 82% C&C WAN GATE ARRAY 3D CC1191Y5B CC1191Y5B-CAF GA20 SENTRY 20 2.0 49% 82% C&C WAN GATE ARRAY 3D CC1194Y5B CC1194Y5B-CAF GA20 SENTRY 20 2.0 52% 86% C&C WAN GATE ARRAY 3D CC1215Y5B CC1215Y5B-CCF GA20 SENTRY 20 2.0 42% 70% C&C WAN GATE ARRAY 3D CC1285Y5B CC1285Y5B-CBF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CC1279Y5B CC1279Y5B-CCF GA20 SENTRY 20 2.0 42% 70% - ------------------------------------------------------------------------------------------------------------------------------------ Division Business Unit AFM Product ID PDI Code Process Flow Sort Test Sort MYA Baseline Die Cost Wafer/Hour Yield Share - ------------------------------------------------------------------------------------------------------------------------------------ C&C WAN GATE ARRAY 3D CC1280Y5B CC1280Y5B-CCF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CC1281Y5B CC1281Y5B-CCF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CC1501Y5B CC1501Y5B-CBF GA20 SENTRY 20 2.0 42% 70% C&C WAN GATE ARRAY 3D CC1510Y5B CC1510Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CC1510Y5B CC1510Y5B-CBF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CC1521Y5B CC1521Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CC1655Y5B CC1655Y5B-CAF GA20 SENTRY 20 2.0 52% 86% C&C WAN GATE ARRAY 3D CD1193Z5B CD1193Z5B-CAF GA20 SENTRY 20 2.0 49% 81% C&C WAN GATE ARRAY 3D CD1251Z5B CD1251Z5B-CCF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CD1259Z5B CD1259Z5B-CAF GA20 SENTRY 20 2.0 44% 74% Exhibit B Product List and Supporting Data - ------------------------------------------------------------------------------------------------------------------------------------ Division Business Unit AFM Product ID PDI Code Process Sort Test Sort MYA Baseline Die Cost Flow Wafer Yield Share /Hour - ------------------------------------------------------------------------------------------------------------------------------------ C&C WAN GATE ARRAY 3D CD1270Z5B CD1270Z5B-CAF GA20 SENTRY 20 2.0 43% 72% C&C WAN GATE ARRAY 3D CD1301Z5B CD1301Z5B-CCF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CD1434Z5B CD1434Z5B-CBF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CD1472Z5B CD1472Z5B-CAF GA20 SENTRY 20 2.0 42% 70% C&C WAN GATE ARRAY 3D CD1520Z5B CD1520Z5B-CBF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CD1693Z5B CD1693Z5B-CAF GA20 SENTRY 20 2.0 44% 73% C&C WAN GATE ARRAY 3D CE1136Y5B CE1136Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CE1435Y5B CE1435Y5B-CBF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CE1471Y5B CE1471Y5B-CBF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CE1609Y5B CE1690Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CE1954Y5B CE1954Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CE1955Y5B CE1955Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CE1956Y5B CE1956Y5B-CAF GA20 SENTRY 20 2.0 N/A N/A C&C WAN GATE ARRAY 3D CI1532Z5B CI1532Z5B-CAF GA20 SENTRY 20 2.0 N/A N/A PSD CGS 4N CGS100B2530A4B CGS100B2530A4B-TAB CGS MCT20XX 2.0 N/A N/A PSD CGS 4N CGS100B2531A4B CGS100B2531A4B-TAB CGS MCT20XX 2.0 N/A N/A PSD CGS 4N CGS2534Z6B CGS2534Z6B-BAB CGS10 MCT20XX 2.0 50% 50% PSD CGS 4N CGS2535Z6B CGS2535Z6B-BAB CGS10 MCT20XX 2.0 50% 50% PSD CGS 4N CGS2536Z6B CGS2536Z6B-BAB CGS10 MCT20XX 2.0 N/A N/A PSD CGS 4N CGS2537Z6B CGS2537Z6B-BAB CGS10 MCT20XX 2.0 50% 50% PSD CGS 4N CGS74B2525Y4B CGS74B2525Y4B-TDB CGS MCT20XX 2.0 N/A N/A PSD CGS 4N CGS74B2528A4B CGS74B2528A4B-TCB CGS MCT20XX 2.0 N/A N/A PSD CGS 4N CGS74B303A4B CGS74B303A4B-TAB CGS MCT20XX 2.0 N/A N/A PSD CGS 4N CGS74B304A4B CGS74B304A4B-TAB CGS MCT20XX 2.0 N/A N/A PSD CGS 4N CGS74B305A4B CGS74B305A4B-TAB CGS MCT20XX 2.0 N/A N/A PSD CGS 4N CGS74CT2524Z5B CGS74CT2524Z5B-CBF CGSP/E MCT20XX 2.0 N/A N/A PSD CGS 4N CGS74CT2525Z5B CGS74CT2525Z5B-CCF CGSP/E MCT20XX 2.0 56% 93% PSD CGS 4N CGS74CT2526Z5B CGS74CT256Z5B-CBF CGSP/E MCT20XX 2.0 50% 83% PSD CGS 4N CGS74C2525Z5B CGS74C2525Z5B-CCF CGSP/E MCT20XX 2.0 50% 83% PSD CGS 4N CGS74C2526Z5B CGS74C2526Z5B-CCF CGSP/E MCT20XX 2.0 N/A N/A PSD DRAM 81 DP8409A4B DP8409A4B-TAA DRAM N/A N/A N/A PSD DRAM 81 DP8410A4B DP8410A4B-TAA DRAM N/A N/A N/A PSD DRAM 81 M632Y4B M632Y4B-TDB DRAM MCT20XX 2.0 41% 68% PSD MASS STORAGE 4H DPC106C5B DPC106C5B-CEA ALS15 MCT20XX 3.0 N/A N/A PSD MASS STORAGE 4H DPC110A5B DPC110A5B-CAA ALS15 MCT20XX 3.0 N/A N/A PSD MASS STORAGE 4H DP84910DC5B DP84910DC5B-CEA ALS15 MCT20XX 3.0 46% 76% YES PSD REAL TIME CLOCK 4C MM48167W4B MM48167W4B-TAA RTCCMOS NATIONAL N/A N/A N/A PSD REAL TIME CLOCK 4C MM48174V4B MM48174V4B-TAA RTCCMOS NATIONAL N/A N/A N/A PSD REAL TIME CLOCK 4C MM48274D4B MM48274D4B-TAA RTCCMOS NATIONAL N/A 42% 70% YES PSD NOTEBOOK H6 PC77336 PC77336-A1A CS080C LTX TRILLIU 2.0 44% 73% YES PSD DESKTOP 6F PC77332E1A PC77332E1A-B CS080C LTX TRILLIU 4.0 44% 73% YES PSD DESKTOP 6F PC77306B1A PC77306B1A-BIBD CS080C LTX TRILLIU 4.0 43% 71% YES PSD DESKTOP 6F PC77306B1A PC77306B1A-BIBR CS080C LTX TRILLIU 4.0 43% 71% YES - - Sort Wafer/Hour numbers reflect Family Level Averages on low running devices. Individual Device UPH will be updated when material is available at Sort. EXHIBIT C PROCESS DEVELOPMENT SCHEDULE The following processes, upon which development is underway, will be regarded as complete when qualification is achieved to Class III, as defined in National specification SOP-5-032 RA. Additional funding will be required from National if programs are not completed due to National's failure to perform its responsibilities by the Scheduled End of Work date. Schedule Process Site Description Completion Funding ------- ---- ----------- ---------- ------- CS080CBIVU Maine BiCMS version of CS080, May 25, 1997 $300K with two layers of metal, isolated NMOS devices and vertical PNP device CS065SE Utah Dense EEPROM variation of May 25, 1997 $300K CS065S, with double poly and double metal As of November 19, 1996, the following processes had not yet achieved Class III qualification, but they are expected to be Class III qualified by February 23, 1997. They are included here for reference only. Scheduled Process Site Description Completion ------- ---- ----------- ---------- ABIC2L Maine ABiC-4 with two layers of metal, with a Product Line mid-flow inventory point for subsequent Dependent ASIC personalization. 0.8(mu) BiCMOS ABIC3L Maine ABiC-4 with three layers of metal, with Product Line a mid-flow inventory point for Dependent subsequent ASIC personalization. 0.8(mu) BiCMOS ABIC4L Maine ABiC-4 with four layers of metal, with Product Line a mid-flow inventory point for Dependent subsequent ASIC personalization. 0.8(mu) BiCMOS ABIC52L Maine ABiC-5 with two layers of metal and Feb. 23, 1997 0.5(mu), three sided emitter, for use in RF products. CMOS remains at 0.8(mu) CS080CBIHY Maine BiCMOS Version of CS080, with two Jan. 19, 1997 layers of metal, isolated NMOS devices, high voltage NPN and Schottky diode CS080CBIP Maine BiCMOS version of CS080, with two Jan. 19, 1997 layers of metal, isolated NMOS devices and double poly capacitor CS80SG Utah Low density EEPROM variation of CS080 Dec. 5, 1996 with double poly and double metal Spec: CS80SG3 Utah Low density EEPROM variation of CS080 Jan. 19, 1997 with double poly and triple metal if product is Spec: available EXHIBIT D CAPACITY REQUEST AND REPSONSE FORMATS ============================================================================ South Portland 4100 FY97 FY97 FY97 FY97 FY98 FY98 FY98 FY98 Per Per Per Per Per Per Per Per 9 10 11 12 1 2 3 4 ==================================================================================== Workdays 34 27 28 35 27 27 35 27 ==============================================---------------------------------------------------------------------------- Starts Forecast by Fab Details: Raw by Size ============================================== ============================================== ANALOG DAP FM584MGCMOS 0 0 0 0 0 0 0 0 ANALOG DAP FMA24MGCMOS 0 0 0 0 0 0 0 0 ANALOG INTERFACE FM4K4BUS 0 0 0 0 0 0 0 0 ANALOG INTERFACE FM804DTP 0 0 0 0 0 0 0 0 ANALOG INTERFACE FMH14DTCOMM 0 0 0 0 0 0 0 0 ANALOG INTERFACE FMH24PTP 0 0 0 0 0 0 0 0 ANALOG INTERFACE FMH24PTPCMOS 0 0 0 0 0 0 0 0 ANALOG Total 4100 0 0 0 0 0 0 0 0 ============================================== ============================================== CCG AUDIO FMA94HV700 0 0 0 0 0 0 0 0 CCG CD FM424ANALOG 0 0 0 0 0 0 0 0 CCG CD FM424ANALOGCMOS 0 0 0 0 0 0 0 0 CCG LAN FM154LAN 0 0 0 0 0 0 0 0 CCG Total 4100 0 0 0 0 0 0 0 0 ============================================== ============================================== PSD DESKTOP FM4C4RTCMOS 0 0 0 0 0 0 0 0 PSD DESKTOP FM4N4CGS 0 0 0 0 0 0 0 0 PSD DESKTOP FM814DRAM 0 0 0 0 0 0 0 0 PSD Total 4100 0 0 0 0 0 0 0 0 ============================================== Grand Total 4100 0 0 0 0 0 0 0 0 =========================================================================== South Portland 4100 FY97 FY97 FY97 FY97 FY98 FY98 FY98 FY98 Per Per Per Per Per Per Per Per 9 10 11 12 1 2 3 4 ======================================================================================= Workdays 34 27 28 35 27 27 35 27 ==================================================--------------------------------------------------------------------------- Starts Forecast by Fab Details: Raw by Size ================================================== ================================================== CCG WAN FM3D5GA20 0 0 0 0 0 0 0 0 CCG Total 5100 0 0 0 0 0 0 0 0 ================================================== ================================================== PSD DESKTOP FM4N5CGSP/E 0 0 0 0 0 0 0 0 PSD DESKTOP FM815ALS15 0 0 0 0 0 0 0 0 PSD MASSSTORAGE FM4H5MASSTOR 0 0 0 0 0 0 0 0 PSD Total 5100 0 0 0 0 0 0 0 0 ================================================== Grand Total 5100 0 0 0 0 0 0 0 0 ============================================================================ South Portland 4100 FY97 FY97 FY97 FY97 FY98 FY98 FY98 FY98 Per Per Per Per Per Per Per Per 9 10 11 12 1 2 3 4 ============================================================================ Workdays 34 27 28 35 27 27 35 27 ==============================================---------------------------------------------------------------------------- Starts Forecast by Fab Details: Raw by Size ============================================== ============================================== ANALOG INTERFACE FM4K680HV 0 0 0 0 0 0 0 0 ANALOG INTERFACE FM4K6BUS 0 0 0 0 0 0 0 0 ANALOG DAP FM586CBIPC 0 0 0 0 0 0 0 0 ANALOG INPUT SIGNAL FM7N6CBIVU 0 0 0 0 0 0 0 0 ANALOG AMPS FM7N6CSO80CBI 0 0 0 0 0 0 0 0 ANALOG INTERFACE FM806CS80CBI 0 0 0 0 0 0 0 0 ANALOG WIRELESS FM9W6ABIC2L 0 0 0 0 0 0 0 0 ANALOG WIRELESS FM9W6ABIC4L 0 0 0 0 0 0 0 0 ANALOG WIRELESS FM9W6ABIC52L 0 0 0 0 0 0 0 0 ANALOG DAP FMA76CBIPC 0 0 0 0 0 0 0 0 ANALOG INTERFACE FMH16CS80C 0 0 0 0 0 0 0 0 ANALOG INTERFACE FMH26CS80C 0 0 0 0 0 0 0 0 ANALOG INTERFACE FMH26CBIHY 0 0 0 0 0 0 0 0 ANALOG COMLINEAR FMR16ABIC2LM 0 0 0 0 0 0 0 0 ANALOG COMLINEAR FMR36ABIC2LM 0 0 0 0 0 0 0 0 ANALOG COMLINEAR FMR46ABIC2LM 0 0 0 0 0 0 0 0 ANALOG Total 6001 0 0 0 0 0 0 0 0 ============================================== ============================================== CCG LAN FM156LANCS65 0 0 0 0 0 0 0 0 CCG LAN FM156LANCS80 0 0 0 0 0 0 0 0 CCG WAN FM896ABIC4L 0 0 0 0 0 0 0 0 CCG WAN RM896ABIC3L 0 0 0 0 0 0 0 CCG CD FM896ABIC2L 0 0 0 0 0 0 0 0 CCG CD FMT9680CBI 0 0 0 0 0 0 0 0 CCG LAN FMX36LAN80CBTX 0 0 0 0 0 0 0 0 CCG Total 6001 0 0 0 0 0 0 0 ============================================== ============================================== PSD DESKTOP FM4N6CGS10 0 0 0 0 0 0 0 PSD DESKTOP FM4NCCS65CBI 0 0 0 0 0 0 0 0 PSD DESKTOP FM4N6CS80CBI 0 0 0 0 0 0 0 0 PSD DESKTOP FM6F6ES80C 0 0 0 0 0 0 0 0 PSD NOTEBOOK FMH66ES80C 0 0 0 0 0 0 0 0 PSD Total 6001 0 0 0 0 0 0 0 0 ============================================== Grand Total 6001 0 0 0 0 0 0 0 0 ============================================================================ South Portland 4100 FY97 FY97 FY97 FY97 FY98 FY98 FY98 FY98 Per Per Per Per Per Per Per Per 9 10 11 12 1 2 3 4 ============================================================================ Workdays 34 27 28 35 27 27 35 27 ==============================================---------------------------------------------------------------------------- Starts Forecast by Fab Details: Raw by Size ============================================== ============================================== ANALOG DAP CS100HE2 0 0 0 0 0 0 0 0 ANALOG INTERFACE CS100HE2 0 0 0 0 0 0 0 0 ANALOG INPUT SIGNAL CS100HE2 0 0 0 0 0 0 0 0 ANALOG POWER MGT CS100HE2 0 0 0 0 0 0 0 0 ANALOG INPUT SIGNAL CS080SG 0 0 0 0 0 0 0 0 ANALOG Total SLC 0 0 0 0 0 0 0 0 ============================================== ============================================== PSD CONTROLLERS CE130 0 0 0 0 0 0 0 PSD CONTROLLERS CE080DLM 0 0 0 0 0 0 0 0 PSD CONTROLLERS CS065SE 0 0 0 0 0 0 0 0 PSD Total SLC 0 0 0 0 0 0 0 0 ============================================== Grand Total LSC 0 0 0 0 0 0 0 0 ============================================================================ South Portland 4100 FY97 FY97 FY97 FY97 FY98 FY98 FY98 FY98 Per Per Per Per Per Per Per Per 9 10 11 12 1 2 3 4 ============================================================================ Workdays 34 27 28 35 27 27 35 27 ==============================================---------------------------------------------------------------------------- Starts Forecast by Fab Details: Raw by Size ============================================== ============================================== SOUTH PORTLAND FM 4100 0 0 0 0 0 0 0 0 SOUTH PORTLAND FM 5100 0 0 0 0 0 0 0 SOUTH PORTLAND FM 6001 0 0 0 0 0 0 0 0 South Portland 0 0 0 0 0 0 0 Subtotal SALT LAKE CITY 6-inch 0 0 0 0 0 0 0 ============================================== Grand Total 0 0 0 0 0 0 0 0 EXHIBIT D Forecasting Timetable ============================================================================================================= Period 12 Period 1 Period 2 Period 12 ------------------------------------------------------------------------------------------------------------- Week 1 2 3 4 5 1 2 3 4 1 2 3 4 1 2 3 4 5 ---------------------------------------------------------------------------------------------------------------------- 1 ------------------------------------------------------------------------------------------------------------- D 2 ZA A A ZA ------------------------------------------------------------------------------------------------------------- A 3 ------------------------------------------------------------------------------------------------------------- Y 4 ------------------------------------------------------------------------------------------------------------- 5 R Y R Y R Y R Y ====================================================================================================================== Actions Defined R National provides 8-period Forecast to Fairchild Y Fairchild provides capacity response to National Z National places blanket, 3-period purchase order with Fairchild A National releases details of wafer starts for the following period. EXHIBIT E DIE COST IMPACT SHARING 1.0 GENERAL 1.1 National and Fairchild will implement 50:50 sharing of yield gain and loss implemented in accordance with the principles set forth in this Exhibit. 1.2 The yield adjustment amount will be calculated at the end of the first six (6) fiscal periods ("Fiscal Half") from the Effective Date and each Fiscal Half thereafter, retroactively. National will pay Fairchild a yield premium fee in the case of average yield improvement; Fairchild will reimburse National in the case of average yield degradation. 1.3 Net Die Per Wafer (NDPW) will be used as the basis for the calculation. 2.0 ESTABLISHING YIELD BASELINE 2.1 In order to qualify for die cost sharing, Products must (i) have achieved a minimum production volume of at least ninety-six (96) Wafers (i.e., the equivalent of at least four (4) 24-Wafer or eight 12-Wafer lots) per period for three (3) of the preceding six (6) fiscal periods (a minimum of 288 Wafers) and (ii) have a stable yield history (e.g., without known yield or test sensitivities). The baseline NDPW of each qualifying Product as of the Effective Date shall be the average NDPW for the preceding six (6) fiscal periods. Baseline NDPWs will be reset twelve (12) fiscal periods ("Fiscal Year") after the Effective Date and at the end of each Fiscal Year thereafter. 2.2 A baseline NDPW will be established for a new Product after the Product has achieved a minimum production volume of at least 96 Wafers per fiscal period (i.e., the equivalent of at least four (4) 24-Wafer or eight 12-Wafer lots) for three (3) of the preceding six (6) fiscal periods (a minimum of 288 Wafers) and (ii) has established a stable yield history (e.g., without known yield or test sensitivities). Once a baseline NDPW has been established for a Product and mutually agreed upon by the Parties, such baseline NDPW will remain in effect until the next Fiscal Year reset point. 2.3 In case of a change in the sort program which affects the yield, a new baseline NDPW will be mutually agreed upon based on the effect of the change on the Product yield. The new baseline will apply to all lots measured after the change has been implemented. 2.4 In the case of a Mask change which affects the yield, a new baseline NDPW will be established as provided in Paragraph 2.2 of this Exhibit. 2.5 For Products that are not sorted by Fairchild the Parties will agree on procedures to assure that production sort programs cannot be changed without Fairchild's acknowledgment, and the provisions of Paragraph 2.3 of this Exhibit shall apply to any such changes. 2.6 In order for a Product that is not sorted by Fairchild to qualify for die cost sharing, National must make wafer sort and yield data, and wafers (at Fairchild's cost) as required for analysis, available to Fairchild on a timely basis and in conformance with Fairchild's own internal requirements for such data. 3.0 CALCULATIONS 3.1 At the end of each Fiscal Half, a Product list to be used for the yield adjustment calculation will be mutually agreed by the Parties. Each Product in this list shall (i) have an established baseline NDPW; (ii) have achieved a minimum production volume of at least ninety-six (96) Wafers per period (i.e., the equivalent of four 24-Wafer or eight 12-Wafer lots) for three (3) of the preceding six (6) fiscal periods (a minimum of 288 Wafers); and (iii) have established a stable yield history (e.g., without known yield or test sensitivities). 3.2 The percent change in NDPW for the preceding Fiscal Half will be calculated for each qualifying Product based on the difference between the baseline and actual NDPW for the Product; 3.3 The semiannual adjustment for die cost sharing will equal: (Base Wafer Price) X (NDPW Percent Change) X (0.5) X (Wafers Shipped) 3.4 The total adjustment will be the sum of the adjustments of the qualifying Products. 3.5 Fairchild will perform the die cost sharing calculation and provide an accounting to National following the end of each Fiscal Half together with an invoice or a credit for the die cost adjustment amount. 4.0 OTHER 4.1 MYA will be used in conjunction with die cost sharing for purposes of identifying "Maverick" wafers that will be discarded (unless National agrees to accept). For Products that qualify for die cost sharing, the baseline NDPW will be used as the basis for defining the MYA for the Product. 4.2 Wafer price adjustments to reflect changes in Fairchild's manufacturing cost base are independent of die cost sharing. 4.3 Products manufactured under the Mil/Aero Wafer and Services Agreement between the Parties of even date herewith shall not qualify for die cost sharing. EXHIBIT F WAFER ACCEPTANCE CRITERIA Fairchild Electrical Test Acceptance Method: Acceptance of Fairchild Wafers for shipment to National shall be determined per mutually agreed upon electrical parameter test distribution performance with standard test die. For the West Jordan, Utah fabs, all wafers will be subjected to the Acceptance Criteria specified in West Jordan specifications: SOP-3060, TS-3020 and TS-3021. For the South Portland, Maine fabs, all Wafers will be tested to the electrical specifications, by Process, listed in this Exhibit, with the acceptance methods stated below. South Portland, Maine Wafer Acceptance and Wafer Sort: 1. Each lot will be sampled at PCM test prior to Wafer sort. The following minimum sample size will be tested and the Wafer will be rejected if the stated number, or more, of test sites on that Wafer fails a specified electrical parameter; Wafer Size #Wafers per lot #Sites per Wafer Reject on #Sites Tested Failing 6 inch 5 5 3 5 inch 5 5 3 4 inch 3 5 3 2. In the event that one or more Wafers in the lot sample fail the above criteria, then 100% testing of the remaining Wafers in the lot will be performed and the above acceptance criteria applied to each Wafer. 3. Electrical Test parameter distributions will be made available to National on a monthly basis. Fairchild Wafer Fabrication and National Wafer Sort: 1. A ten (10) Wafer lot sample will be tested to the applicable PCM specification prior to shipment to National. Five (5) test sites per wafer will be sampled as the basis for electrical acceptance, and three (3) of those sites must pass the PCM test parameters. In the event that one or more sample wafers fails the PCM tests, 100% testing of residual wafers will be performed and all Wafers which pass the PCM will be shipped to National. 2. Individual PCM specifications (by Process) are defined in Exhibit F. 3. Electrical Test parameter distributions will be made available on a monthly basis. Fairchild Maine Fab 4100: "ANALOG" - ---------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - ---------------------------------------------------------------------------------------------------------------------------- Bjt NPN BETA Q2Beta 50 150 250 Gain Ic=1mA, Vce=5.0V Bjt NPN CBO Q2BVcbo 50 >50 N/A Volts If-10uA Bjt NPN EBO Q2BVebo 6.5 7.0 7.5 Volts If=10uA Bjt NPN CEO Q2LVceo 15 >15 N/A Volts If=10uA Bjt Col to Col BV_iso 50 >50 N/A Volts If=5uA - ---------------------------------------------------------------------------------------------------------------------------- Diffusion N Buried Layer BL_RES 75 110 150 Ohms If=10mA Diffusion Narrow Base N_RES 800 1000 1800 Ohms If=1mA Diffusion Base BASERHO 100 125 150 Ohms/sq If=4.53mA Diffusion Emitter N+RHO 3.0 4.5 6.0 Ohms/sq If=45.3mA - ---------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 4100: "BUS" - ---------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - ---------------------------------------------------------------------------------------------------------------------------- Bjt NPN BETA Q1Beta 20 100 225 Gain Ic=1mA, Vce=5.0V Bjt NPN CBO Q1BVcbo 20 >20 N/A Volts If-10uA Bjt NPN EBO Q1BVebo 6.7 8.0 8.3 Volts If=10uA Bjt NPN CEO Q1LVceo 8.0 >8 N/A Volts If=10uA Bjt Col to Col BV_iso 7.5 >7.5 N/A Volts If=5uA - ---------------------------------------------------------------------------------------------------------------------------- Diffusion N Buried Layer BLres1 30 45 100 Ohms If=10mA Diffusion Narrow Base Narbase 1900 2500 2900 Ohms If=1mA Diffusion Emitter EM-res 5.0 10 40 Ohms/sq If=10mA - ---------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 4100: "CGS" Table of Parameters not available on January 2, 1997. Fairchild Maine Fab 4100: "DRAM" - -------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - -------------------------------------------------------------------------------------------------------------------------- Bjt CEO MinLVCEO1 5.5 20 Volts - -------------------------------------------------------------------------------------------------------------------------- Bjt CBO MinBVCBO 18 30 Volts - -------------------------------------------------------------------------------------------------------------------------- Bjt EBO MinBVEBO 3.5 10 Volts - -------------------------------------------------------------------------------------------------------------------------- Bjt Beta MinBeta1 75 200 Gain - -------------------------------------------------------------------------------------------------------------------------- Diffusion Base BaseRho 562 688 Ohms/sq. - -------------------------------------------------------------------------------------------------------------------------- Diffusion Resistor RES-RHO 1800 2200 Ohms/sq. - -------------------------------------------------------------------------------------------------------------------------- Via Via 2048VIA 2048 via link 0 155 Ohms - -------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 4100: "DTCOMM - -------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - -------------------------------------------------------------------------------------------------------------------------- Bjt NPN BETA Q3Beta 80 180 250 Gain Ic-10mA, Vce=2.5V - -------------------------------------------------------------------------------------------------------------------------- Bjt NPN CBO Q3BVcbo 38 >38 N/A Volts If=100uA - -------------------------------------------------------------------------------------------------------------------------- Bjt NPN EBO Q3BVebo 5.5 6.3 7.0 Volts If=100uA - -------------------------------------------------------------------------------------------------------------------------- Bjt NPN CEO Q3LVceo 5.0 >5 N/A Volts If=5uA - -------------------------------------------------------------------------------------------------------------------------- Bjt Col to Col BV_ISO 15 >15 N/A Volts If=100uA - -------------------------------------------------------------------------------------------------------------------------- Diffusion N Buried R_BL 15 23 30 Ohms If=50mA Layer - -------------------------------------------------------------------------------------------------------------------------- Diffusion Narrow Base R_NB 1650 2100 2500 Ohms If=100uA - -------------------------------------------------------------------------------------------------------------------------- Diffusion Emitter R_EM 100 150 200 Ohms If=10mA - -------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 4100: "DTP" - ----------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - ----------------------------------------------------------------------------------------------------------------------- Bjt CEO Q1LVCEO 7 15 30 Volts - ----------------------------------------------------------------------------------------------------------------------- Bjt CBO Q1BVCBO 30 45 80 Volts - ----------------------------------------------------------------------------------------------------------------------- Bjt EBO Q1BVEBO 6 6.8 7.5 Volts - ----------------------------------------------------------------------------------------------------------------------- Bjt Beta Q1Beta 75 150 350 Gain - ----------------------------------------------------------------------------------------------------------------------- Bjt Schottky Q4VFD 0.26 0.32 0.4 Volts - ----------------------------------------------------------------------------------------------------------------------- Bjt Schottky BVSKY 10 20 40 Volts - ----------------------------------------------------------------------------------------------------------------------- Diffusion Base BaseRho 160 190 220 Ohms/sq. - ----------------------------------------------------------------------------------------------------------------------- Diffusion Collector BL-RES 75 110 135 Ohms - ----------------------------------------------------------------------------------------------------------------------- Diffusion Resistor IMP-RES 13K 16K 19K Ohms - ----------------------------------------------------------------------------------------------------------------------- Diffusion Emitter N+RHO 4.25 5 5.75 Ohms/sq. - ----------------------------------------------------------------------------------------------------------------------- Diffusion Resistor N-RES 1250 1525 1800 Ohms - ----------------------------------------------------------------------------------------------------------------------- Diffusion Sink SINK-RES 6 8.5 11 Ohms - ----------------------------------------------------------------------------------------------------------------------- Farichild Maine Fab 4100: "LAN" - -------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - -------------------------------------------------------------------------------------------------------------------------- Bjt Beta Q3BETA Ae=4.6 sq 70 140 300 Gain Ic=10mA, Vce=2.5V mils - -------------------------------------------------------------------------------------------------------------------------- Bjt CBO Q3BVCBO Ae=4.6 sq >20 43 N/A Volts If=100uA mils - -------------------------------------------------------------------------------------------------------------------------- Bjt CEO Q3LVCEO Ae=4.6 sq >10 20 N/A Volts If=5uA mils - -------------------------------------------------------------------------------------------------------------------------- Diff Res R_EM(R12) 0.5X10 sq 150 210 270 Ohms If=10mA - -------------------------------------------------------------------------------------------------------------------------- Diff Res R_NB(R10) 0.3X10 sq 1600 2075 2550 Ohms If=100uA - -------------------------------------------------------------------------------------------------------------------------- Impl Res RNI_RI4 0.5X10 sq 8000 10000 12000 Ohms If=100uA - -------------------------------------------------------------------------------------------------------------------------- Via Via VIA400 5um x 5um 17 21 26 Ohms If=1mA - -------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 4100: "PTP" - -------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - -------------------------------------------------------------------------------------------------------------------------- Bjt NPN Beta Q3BETA 15 50 100 Gain Ic=1mA, Vce=5.0V - -------------------------------------------------------------------------------------------------------------------------- Bjt NPN CBO Q3BVCBO 10 35 100 Volts Ie=10uA - -------------------------------------------------------------------------------------------------------------------------- Bjt NPN EBO Q3BVEBO 6.5 7 7.5 Volts Ie=10uA - -------------------------------------------------------------------------------------------------------------------------- Bjt NPN CEO Q3LVCEO 7 35 60 Volts Ic=10uA - -------------------------------------------------------------------------------------------------------------------------- Bjt Col to Col BV_ISO 30 70 100 Volts I=5uA - -------------------------------------------------------------------------------------------------------------------------- Diffusion N Buried BL_RES 90 115 140 Ohms I=10mA Layer - -------------------------------------------------------------------------------------------------------------------------- Diffusion Sink(Plug) SINK_RES 2 12 30 Ohms I=10mA - -------------------------------------------------------------------------------------------------------------------------- Diffusion Emitter N+RHO 3.5 6 7 Ohms/sq I=4.53mA - -------------------------------------------------------------------------------------------------------------------------- Diffusion Base BASERHO 170 195 220 Ohms/sq I-4.53mA - -------------------------------------------------------------------------------------------------------------------------- Diffusion Narrow Base N-RES 1250 1625 2000 Ohms I-1mA - -------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 4100: "PTPCMOS" - -------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - -------------------------------------------------------------------------------------------------------------------------- MOS Vtp VTOP_SHORT -1.3 -0.85 -0.4 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Bvdp BVDSP_SHORT -50 -25 0 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Vtn VTON_SHORT 0.4 0.65 0.9 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Bvdn BVDSN_SHORT 18 39 60 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Idsat IDP_5.0/5.0_SHORT -2 -1.5 -1 mAmps - -------------------------------------------------------------------------------------------------------------------------- MOS Idsat IDN_5.0/5.0_SHORT 2 3.5 5 mAmps - -------------------------------------------------------------------------------------------------------------------------- Diffusion N+ N+_RES 2 8 14 Ohms/sq. - -------------------------------------------------------------------------------------------------------------------------- Diffusion P- P-_RES 3 5 7 Ohms/sq. - -------------------------------------------------------------------------------------------------------------------------- Diffusion P+ P+_RES 30 55 80 Ohms/sq. - -------------------------------------------------------------------------------------------------------------------------- Via Contact P+_CONT_RES 0 25 50 Ohms/cnt. - -------------------------------------------------------------------------------------------------------------------------- Via Contact N+_CONT_RES 0 7 30 Ohms/cnt. - -------------------------------------------------------------------------------------------------------------------------- Yd Gate BV_GATE_OXIDE -200 -125 -50 Volts Oxide - -------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 4100: "RTCCMOS" - -------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - -------------------------------------------------------------------------------------------------------------------------- MOS Vtp VTOP_SHORT -1.5 -0.875 -0.25 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Bvdp BVDSP_SHORT -50 -25 0 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Vtn VTON_SHORT 0.3 0.65 1 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Bvdn BVDSN_SHORT 18 39 60 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Idsat IDP_5.0/5.0_SHORT -2 -1.3 -0.6 mApms - -------------------------------------------------------------------------------------------------------------------------- MOS Idsat IDN_5.0/5.0_SHORT 3 4 5 mAmps - -------------------------------------------------------------------------------------------------------------------------- Diffusion N+ N+_RES 2 8 14 Ohms/sq. - -------------------------------------------------------------------------------------------------------------------------- Diffusion P- P-_RES 4 6.5 9 Ohms/sq. - -------------------------------------------------------------------------------------------------------------------------- Diffusion P+ P+_RES 30 55 80 Ohms/sq. - -------------------------------------------------------------------------------------------------------------------------- Via Contact P+_CONT_RES 0 20 40 Ohms/cnt. - -------------------------------------------------------------------------------------------------------------------------- Via Contact N+_CONT_RES 0 15 30 Ohms/cnt. - -------------------------------------------------------------------------------------------------------------------------- Yd Gate BV_GATE_OXIDE -200 -125 -50 Volts Oxide - -------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 5100: "GA20" - -------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - -------------------------------------------------------------------------------------------------------------------------- MOS Vtp VTOP2 -1 -0.8 -0.6 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Bvdp BVDSSP2 -20 -13.09 -7 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Vtn VTON2 0.6 0.75 0.9 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Bvdn BVDSSN2 7 12 20 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Idsat IDSSP2 -0.004 -0.003 -0.0012 mAmps - -------------------------------------------------------------------------------------------------------------------------- MOS Idsat IDSSN2 0.0032 0.005 0.0072 mAmps - -------------------------------------------------------------------------------------------------------------------------- Via Contact CONTM1M2 0 0.07 0.15 Ohms/cnt - -------------------------------------------------------------------------------------------------------------------------- Via Contact CONTMP+ 1000 7500 20000 Ohms/cnt. - -------------------------------------------------------------------------------------------------------------------------- Via Contact CONTMN+ 1000 4000 10000 Ohms/cnt. - -------------------------------------------------------------------------------------------------------------------------- Yd Gate BVGOXP 20 24 30 Volts Oxide - -------------------------------------------------------------------------------------------------------------------------- Yd Gate BVGOXN -30 -26 -22 Volts Oxide - -------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 5100: "ALS15" - -------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - -------------------------------------------------------------------------------------------------------------------------- MOS Field vt FIELD_VT 10 25 40 Volts Id=1uA, Vg=Vd - -------------------------------------------------------------------------------------------------------------------------- Bjt PNP Beta BETA_Q7_50 6X7 Em, 3um 20 50 80 Gain Ic=50uA, Vce=2.5V P+/P+ - -------------------------------------------------------------------------------------------------------------------------- Bjt NPN Beta LOP2B_20UA (5X32)X2 70 110 180 Gain Ic=20uA, Vce=2.0V E-Stripes - -------------------------------------------------------------------------------------------------------------------------- Bjt NPN EBO 20K_EBO 20K 2X2 Em grid 4 5 15 Volts Ie=10uA - -------------------------------------------------------------------------------------------------------------------------- Bjt NPN CEO AREA_CEO 500X500 Em 1 6 25 Volts Ic=10uA - -------------------------------------------------------------------------------------------------------------------------- Diffusion N Buried BLR_RHO 50X50 20.5 23 27 Ohms/sq I=10mA Layer - -------------------------------------------------------------------------------------------------------------------------- Diffusion Sink(Plug) SINK_RHO 48X48 13 16 20 Ohms/sq I=10mA - -------------------------------------------------------------------------------------------------------------------------- Diffusion P- P-_30X3 (L/W)30X3 1500 1650 1850 Ohms/sq V=0.1V - -------------------------------------------------------------------------------------------------------------------------- Diffusion P+ P+_30X3 (L/W)30X3 150 175 200 Ohms/sq V=0.1V - -------------------------------------------------------------------------------------------------------------------------- Schottky Vf VS_D5 1300 um sq 0.51 0.54 0.58 Volts Ib-300uA (GRring) - -------------------------------------------------------------------------------------------------------------------------- Schottky Vr VR_D5 1300 um sq 18 25 35 Volts Ic-10uA (GRing) - -------------------------------------------------------------------------------------------------------------------------- Via M2 Via RES_VIACHN 90 110 130 Ohms I=1mA - -------------------------------------------------------------------------------------------------------------------------- Via P-Contact PCON_RES 100 2X2 P+ 5000 6000 7000 Ohms I=100uA Contacts - -------------------------------------------------------------------------------------------------------------------------- Via N-Contract NCON_RES 100 2X2 Sink 180 225 300 Ohms 1=100uA Contacts - -------------------------------------------------------------------------------------------------------------------------- Metal Rs Metal 1 M1SNAKE 2500 2850 3200 Ohms V=0.1V - -------------------------------------------------------------------------------------------------------------------------- Metal Rs Metal 2 M2SNAKE 200 275 350 Ohms V-0.1V - -------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 5100: "CGSP/E" Table of parameters to be defined. Fairchild Maine Fab 6001: "ABiC2L & ABiC2LM" - ---------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - ---------------------------------------------------------------------------------------------------------------------------- MOS Vtn VTO_N840 W/L 40/0.8 0.6 0.75 0.9 Volts Linear Extrapolation (Vd=0.1V, Vb=Vs=GND) - ---------------------------------------------------------------------------------------------------------------------------- MOS Idsat IDS5N840 W/L 40/0.8 0.32 0.4 0.48 mA/um Vg=Vd=5.0V, Vb=Vs=GND - ---------------------------------------------------------------------------------------------------------------------------- MOS Bvdn BVDSN840 W/L 40/0.8 7 >7 Volts Vg=Vb=Vs=GND, Id=1uA/um - ---------------------------------------------------------------------------------------------------------------------------- MOS Vtp VTO_P840 W/L 40/0.8 0.85 1 1.15 Volts Linear Extrapolation (Vd=0.1V, Vb=Vs=GND) - ---------------------------------------------------------------------------------------------------------------------------- MOS Idsat IDS5P840 W/L 40/0.8 0.16 0.2 0.24 mA/um Vg-Vd-5.0V, Vb=Vs=GND - ---------------------------------------------------------------------------------------------------------------------------- MOS Bvdp BVDSP840 W/L 40/0.8 7 >7 Volts Vg=Vb=Vs=GND, Id=1uA/um - ---------------------------------------------------------------------------------------------------------------------------- Bjt CEO CEO_ECL (12-2X12)X2 6 >6 Volts Ic=500uA=1uA/um^2 E-Stripes - ---------------------------------------------------------------------------------------------------------------------------- Bjt CBO CBO_ECL (12-2X12)X2 10 >10 Volts Ic=50uA=0.1uA/um^2 E-Stripes - ---------------------------------------------------------------------------------------------------------------------------- Bjt EBO EBO_ECL (12-2X12)X2 5 >5 Volts Ie=50uA=0.1uA/um^2 E-Stripes - ---------------------------------------------------------------------------------------------------------------------------- Bjt Vbe VBE_ECL (12-2X12)X2 0.75 0.8 0.85 Volts Ie-10mA Vcb-0v E-Stripes (20uA/um^2) - ---------------------------------------------------------------------------------------------------------------------------- Bjt Beta B2C_ECL (12-2X12)X2 50 90 200 Volts Ie=10mA, Vce=2.75v E-Stripes (20uA/um^2) - ---------------------------------------------------------------------------------------------------------------------------- Poly Resistor N+ V_POLYNP VDP 66 75 84 Ohms/sq. I=5mA - ---------------------------------------------------------------------------------------------------------------------------- Poly Resistor P+ V_POLYPP VDP 238 270 320 Ohms/sq. I=5mA - ---------------------------------------------------------------------------------------------------------------------------- Poly Resistor P- V_POLYPM VDP 1190 1400 1610 Ohms/sq. I=1mA - ---------------------------------------------------------------------------------------------------------------------------- Silicide Silicided SILPPRHO VDP 1 2 3 Ohms/sq. I=5ma P+ Poly - ---------------------------------------------------------------------------------------------------------------------------- Diffusion N Buried V_CUO VDP 23.8 32.2 Ohms/sq. I=5mA Layer - ---------------------------------------------------------------------------------------------------------------------------- Diffusion Sink SINKRHO 50X10 45 65 85 Ohms/sq. I=5mA, Calculated ohms/sq. - ---------------------------------------------------------------------------------------------------------------------------- Via Contact CN_CONOX 756 0 7 Ohms/Link I=100uA, Calculated contacts ohms per link - ---------------------------------------------------------------------------------------------------------------------------- Via M2 Via CN_VIAO 756 0 2 Ohms/Link I=1mA, Calculated contacts ohms per link - ---------------------------------------------------------------------------------------------------------------------------- Metal Rs Metal 1 M1_SNKT 18000 490 550 900 Ohms I-1mA, Chain linear um Resistance - ---------------------------------------------------------------------------------------------------------------------------- Metal Rs Metal 22LM M2_SNKT 18000 300 350 550 Ohms I=1mA, Chain linear um Resistance - ---------------------------------------------------------------------------------------------------------------------------- Yd Gate Oxide GOXNWBV 90000 um^2 12 >12 Volts I=1uA - ---------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 6001: "ABiC3L & ABiC4L" Table of Parameters to be defined, because process development is not yet complete. Fairchild Maine Fab 6001: "ABiC52L" Table of Parameters to be defined, because process development is not yet complete. Fairchild Maine Fab 6001: "BUS & CGS10" - -------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - -------------------------------------------------------------------------------------------------------------------------- MOS Vtn VTON1 0.4 0.65 0.9 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Vtp VTOP1 -1.45 -1.05 -0.65 Volts - -------------------------------------------------------------------------------------------------------------------------- MOS Idsat IDSSP1 -0.014 -0.01 -0.005 mA - -------------------------------------------------------------------------------------------------------------------------- MOS Idsat IDSSN1 0.015 0.022 0.029 mA - -------------------------------------------------------------------------------------------------------------------------- MOS Bvdn BVDSSN1 7 13 19 Volts - -------------------------------------------------------------------------------------------------------------------------- Bjt CEO OUTLVCEO 4 5.7 20 Volts - -------------------------------------------------------------------------------------------------------------------------- Bjt CBO OUTBVCBO 14 19 25 Volts - -------------------------------------------------------------------------------------------------------------------------- Bjt EBO OUTBVEBO 3 4.5 5.5 Volts - -------------------------------------------------------------------------------------------------------------------------- Bjt Beta OUTBETA 65 115 200 Volts - -------------------------------------------------------------------------------------------------------------------------- Bjt Schottky VCSCHOTTKY 0.2 0.34 0.475 Volts - -------------------------------------------------------------------------------------------------------------------------- Diffusion Base BASERRES 2300 3200 3700 Ohms - -------------------------------------------------------------------------------------------------------------------------- Diffusion Buried Layer BLRHO 18 28 38 Ohms/sq. - -------------------------------------------------------------------------------------------------------------------------- Diffusion Sink SINKRHO 45 55 65 Ohms/sq. - -------------------------------------------------------------------------------------------------------------------------- Via Contact CONTM1M2 0 0.04 0.075 Ohms/Link - -------------------------------------------------------------------------------------------------------------------------- Contact N+ Contact CONTMN+ 10 30 60 Ohms/Link - -------------------------------------------------------------------------------------------------------------------------- Contact P+ Contact CONTMP+ 10 25 40 Ohms/Link - -------------------------------------------------------------------------------------------------------------------------- Metal Rs Metal 1 M1CONT 0 85 200 Ohms - -------------------------------------------------------------------------------------------------------------------------- Metal Rs Metal 2 M2CONTWC 0 23 70 Ohms - -------------------------------------------------------------------------------------------------------------------------- Yd Gate Oxide BVGOXN -20 -15.5 -12.5 Volts - -------------------------------------------------------------------------------------------------------------------------- Yd Gate Oxide BVGOXP 11.5 13.5 20 Volts - -------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 6001: "CS080C" - -------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - -------------------------------------------------------------------------------------------------------------------------- MOS Vtn N5_VTO W/L 40/0.8 0.6 0.725 0.85 Volts Linear Extrapolation (Vd=0.1V, Vb=Vs=GND) - -------------------------------------------------------------------------------------------------------------------------- MOS Idsat N5_IDSS W/L 40/0.8 13.6 16.8 20 mA Vg=Vd=5.0v, Vb=Vs=GND - -------------------------------------------------------------------------------------------------------------------------- MOS Bvdn N5_BVDSS W/L 40/0.8 10 13.5 17 Volts Vg=Vb=Vs=GND, Id=1uA - -------------------------------------------------------------------------------------------------------------------------- MOS Vtp P5_VTO W/L 40/0.8 -1.1 -0.95 -0.8 Volts Linear Extrapolation (Vd=-0.1V, Vb=Vs=GND) - -------------------------------------------------------------------------------------------------------------------------- MOS Idsat P5_IDSS W/L 40/0.8 -9.2 -7.2 -5.6 mA Vg-Vd-5.0v, Vb=Vs=GND - -------------------------------------------------------------------------------------------------------------------------- MOS Bvdn P5_BVDSS W/L 40/0.8 -15 -12.5 -10 Volts Vg=Vb=Vs=GND, Id=1uA - -------------------------------------------------------------------------------------------------------------------------- Via Contact RM1N_RES M1/N+ Chain 0 250000 500000 Ohms Vf=5.0v - -------------------------------------------------------------------------------------------------------------------------- Via Contact RM1P_RES M1/P+ Chain 0 300000 600000 Ohms Vf=-5.0v - -------------------------------------------------------------------------------------------------------------------------- Via M2 Via RVIAH_RES Via Chain 0 5000 18000 Ohms Vf-5.0v - -------------------------------------------------------------------------------------------------------------------------- Diffusion N-Well RNW1_RES N- in 1000 2000 3000 Ohms Vf=1v Composite - -------------------------------------------------------------------------------------------------------------------------- Diffusion P-Well RPSUB2_RES P- in 70 110 150 Ohms Vf=-1v Composite - -------------------------------------------------------------------------------------------------------------------------- Diffusion N+ RDIFFN1_RES N+ Diffusion 570 750 930 Ohms Vf=1v in P-Well - -------------------------------------------------------------------------------------------------------------------------- Diffusion P+ RDIFFP1_RES P+ Diffusion 1260 1400 1580 Ohms Vf=-1v in N-Well - -------------------------------------------------------------------------------------------------------------------------- Yd Gate Oxide GOXN_BVD 99870um2 -22 -12 -10 Volts If=1ua Poly Cap - -------------------------------------------------------------------------------------------------------------------------- Yd Gate Oxide GOXP_BVD 99840um2 10 12 22 Volts If=1ua Poly Cap - -------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 6001: "CS080CBI" Table of parameters to be defined. Fairchlid Maine Fab 6001: "CS080CBTX" - -------------------------------------------------------------------------------------------------------------------------- Category Parameter Analog Device Size Lower Spec Target Upper Spec Unit Measurement Method - -------------------------------------------------------------------------------------------------------------------------- MOS Vtn N5_VTO W/L 40/0.8 0.6 0.725 0.85 Volts Linear Extrapolation (Vd=0.1V, Vb=Vs=GND) - -------------------------------------------------------------------------------------------------------------------------- MOS Idsat N5_IDSS W/L 40/0.8 13.6 16.8 20 mA Vg=Vd=5.0v, Vb=Vs=GND - -------------------------------------------------------------------------------------------------------------------------- MOS Bvdn N5_BVDSS W/L 40/0.8 10 13.5 17 Volts Vg=Vb=Vs=GND, Id=1uA - -------------------------------------------------------------------------------------------------------------------------- MOS Vtp P5_VTO W/L 40/0.8 -1.1 -0.95 -0.8 Volts Linear Extrapolation (Vd=0.1V, Vb=Vs=GND) - -------------------------------------------------------------------------------------------------------------------------- MOS Idsat P5_IDSS W/L 40/0.8 -9.2 -7.2 -5.6 mA Vg=Vd=5.0v, Vb=Vs=GND - -------------------------------------------------------------------------------------------------------------------------- MOS Bvdn P5_BVDSS W/L 40/0.8 -15 -12.5 -10 Volts Vg=Vb=Vs=GND, Id=1uA - -------------------------------------------------------------------------------------------------------------------------- Via Contact RM1N_RES M1/N+ Chain 00 250000 500000 Ohms Vf=5.0v - -------------------------------------------------------------------------------------------------------------------------- Via Contact RM1P_RES M1P+ Chain 0 300000 600000 Ohms Vf=-5.0v - -------------------------------------------------------------------------------------------------------------------------- Via M2 Via RVIAH_RES Via Chain 0 5000 18000 Ohms Vf=5.0v - -------------------------------------------------------------------------------------------------------------------------- Diffusion N-Well RNW1_RES N-in 1000 2000 3000 Ohms Vf-1v Composite - -------------------------------------------------------------------------------------------------------------------------- Diffusion P-Well RPSUB2_RES P-in 70 110 150 Ohms Vf=-1v Composite - -------------------------------------------------------------------------------------------------------------------------- Diffusion N+ RDIFFN1_RES N+ 570 750 930 Ohms Vf-1v Diffusion in P-Well - -------------------------------------------------------------------------------------------------------------------------- Diffusion P+ RDIFFP1_RES P+ 1260 1400 1580 Ohms Vf=-1v Diffusion in N-Well - -------------------------------------------------------------------------------------------------------------------------- Yd Gate Oxide GOXN_BVD 99870um2 -22 -12 -10 Volts If=-1ua Poly Cap - -------------------------------------------------------------------------------------------------------------------------- Yd Gate Oxide GOXP_BVD 99840um2 10 12 22 Volts If=1ua Poly Cap - -------------------------------------------------------------------------------------------------------------------------- Diffusion Base RBU Vander Pau 1100 1330 1550 Ohms/Sq Calculated Ohms/sq - -------------------------------------------------------------------------------------------------------------------------- Diffusion Buried Layer RBLU Vander Pau 23 29 35 Ohms/Sq Calculated Ohms/sq - -------------------------------------------------------------------------------------------------------------------------- BJT Beta NPN1_BF100U 2.24ux2.08um 35 70 115 Ie=100uA, Vce=1.0v - -------------------------------------------------------------------------------------------------------------------------- BJT CBO NPN1_BVCBO 2.24ux2.08um 10 16.8 20 Volts Ic=1uA, Vb=GND - -------------------------------------------------------------------------------------------------------------------------- BJT EBO NPN1_BVEBO 2.24ux2.08um 5.5 5.75 6.1 Volts Ie=1uA, Vb=GND - -------------------------------------------------------------------------------------------------------------------------- BJT CEO Q1_VCEO 2.24ux2.08um 5.5 7 10 Volts Ve=-100uA, Vc=GND - -------------------------------------------------------------------------------------------------------------------------- Fairchild Maine Fab 6001: "CS080CBIHY" Table of Parameters to be defined, because process development is not yet completed. Fairchld Maine Fab 6001: "CS080CBIP Table of Parameters to be defined, because process development is not yet completed. Fairchild Maine Fab 6001: "CS080CBIVU" Table of Parameters to be defined, because process development is not yet completed. EXHIBIT G PRICES FOR WAFER SORT AND EPI PROCESSING South Portland, Maine Wafer Sort Cost [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION OMITTED AND [CONFIDENTIAL INFORMATION FILED SEPARATELY WITH THE OMITTED AND FILED SECURITIES AND EXCHANGE COMMISSION] SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION OMITTED AND [CONFIDENTIAL INFORMATION FILED SEPARATELY WITH THE OMITTED AND FILED SECURITIES AND EXCHANGE COMMISSION] SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION OMITTED AND [CONFIDENTIAL INFORMATION FILED SEPARATELY WITH THE OMITTED AND FILED SECURITIES AND EXCHANGE COMMISSION] SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] Penang, Malaysia Wafer Sort Cost [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION [CONFIDENTIAL INFORMATION OMITTED OMITTED AND FILED SEPARATELY AND FILED SEPARATELY WITH THE WITH THE SECURITIES AND SECURITIES AND EXCHANGE EXCHANGE COMMISSION] COMMISSION] West Jordan, Utah Wafer Sort Cost [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION [CONFIDENTIAL INFORMATION OMITTED OMITTED AND FILED SEPARATELY AND FILED SEPARATELY WITH THE WITH THE SECURITIES AND SECURITIES AND EXCHANGE EXCHANGE COMMISSION] COMMISSION] Non-recurring costs [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION [CONFIDENTIAL INFORMATION OMITTED OMITTED AND FILED SEPARATELY AND FILED SEPARATELY WITH THE WITH THE SECURITIES AND SECURITIES AND EXCHANGE EXCHANGE COMMISSION] COMMISSION] [CONFIDENTIAL INFORMATION [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY OMITTED AND FILED WITH THE SECURITIES AND SEPARATELY WITH THE EXCHANGE COMMISSION] SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION [CONFIDENTIAL INFORMATION OMITTED OMITTED AND FILED SEPARATELY AND FILED SEPARATELY WITH THE WITH THE SECURITIES AND SECURITIES AND EXCHANGE EXCHANGE COMMISSION] COMMISSION] [CONFIDENTIAL INFORMATION [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY OMITTED AND FILED WITH THE SECURITIES AND SEPARATELY WITH THE EXCHANGE COMMISSION] SECURITIES AND EXCHANGE COMMISSION] Sort Operating Principles FAIRCHILD will load the South Portland, Maine, West Jordan, Utah and Penang, Malaysia Wafer Sort facilities in a manner that minimizes the total costs to NATIONAL, while generating the best possible yield control for NATIONAL Products. This means that Penang will be the primary sorting site for those Products which can be sorted there, unless otherwise instructed by NATIONAL. on a case by case basis, FAIRCHILD will provide NATIONAL the opportunity to install NATIONAL's automatic test equipment within FAIRCHILD's Facilities, which might be required to take advantage of FAIRCHILD's Integrated Yield Management services. FAIRCHILD will quote hourly rates for operations, maintenance and support services, and NATIONAL will assume the costs of equipment depreciation, spare parts, initial setup, probe cards, and electrical interface boards. New sort hardware setups or Wafer sort for new Products In the case of new hardware setups or Wafer sort for new Products, if the hardware and/or test program is provided by National, Fairchild will connect the hardware and/or test program and attempt to sort wafers. If engineering problems are found then Fairchild will debug and solve the problems to the extent of its capabilities utilizing Best Efforts. Epitaxial Layer Processing [CONFIDENTIAL INFORMATION OMITTED AND [CONFIDENTIAL INFORMATION FILED SEPARATELY WITH THE SECURITIES OMITTED AND FILED SEPARATELY AND EXCHANGE COMMISSION] WITH THE SECURITIES AND EXCHANGE COMMISSION] EXHIBIT J OPERATIONAL SUPPORT SERVICES AND FEES The following Operational Support Services can be provided by Fairchild to National for a fee. If no fee is stated it will be negotiated by the Parties at a future date. Production Control Management and Scheduling for National Product lines Mask Making Services: Price - --------------------- ----- Prefracture Edits to Database [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] Reticle Generation [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] Database Fracture [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] Product Specific Test Pattern Modules [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] DRC Verification, up to 20 hours effort [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] for time in excess of 20 hours [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] Database Conversion and Boolean [CONFIDENTIAL INFORMATION OMITTED Operations AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] for time in excess of 50 hours [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] Mathematical Modeling and Characterization Services: Price Per [CONFIDENTIAL Minimum --------- ------- INFORMATION OMITTED AND [CONFIDENTIAL FILED SEPARATELY WITH INFORMATION THE SECURITIES AND OMITTED AND EXCHANGE COMMISSION] FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] Process Circuit Model File [CONFIDENTIAL [CONFIDENTIAL Generation INFORMATION OMITTED AND INFORMATION FILED SEPARATELY WITH OMITTED AND THE SECURITIES AND FILED SEPARATELY EXCHANGE COMMISSION] WITH THE SECURITIES AND EXCHANGE COMMISSION] Analog Specific Parameter [CONFIDENTIAL [CONFIDENTIAL Information INFORMATION OMITTED AND INFORMATION FILED SEPARATELY WITH OMITTED AND THE SECURITIES AND FILED SEPARATELY EXCHANGE COMMISSION] WITH THE SECURITIES AND EXCHANGE COMMISSION] Enhanced Electrical Testing [CONFIDENTIAL [CONFIDENTIAL for New Designs INFORMATION OMITTED AND INFORMATION FILED SEPARATELY WITH OMITTED AND THE SECURITIES AND FILED SEPARATELY EXCHANGE COMMISSION] WITH THE SECURITIES AND EXCHANGE COMMISSION] Geom-Gen and Cadence Symbol [CONFIDENTIAL [CONFIDENTIAL Generation INFORMATION OMITTED AND INFORMATION FILED SEPARATELY WITH OMITTED AND THE SECURITIES AND FILED SEPARATELY EXCHANGE COMMISSION] WITH THE SECURITIES AND EXCHANGE OMMISSION] Automatic Test Equipment Development Services: Price Per [CONFIDENTIAL Minimum --------- ------- INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] MCT20xx Test Program Creation [CONFIDENTIAL [CONFIDENTIAL INFORMATION OMITTED AND INFORMATION FILED SEPARATELY WITH OMITTED AND FILED THE SECURITIES AND SEPARATELY WITH EXCHANGE COMMISSION] THE SECURITIES AND EXCHANGE COMMISSION] MCT20xx Custom Test Solution [CONFIDENTIAL INFORMATION OMITTED AND Development FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] Test Program Port to LTX [CONFIDENTIAL [CONFIDENTIAL MicroMaster System INFORMATION OMITTED AND INFORMATION FILED SEPARATELY WITH OMITTED AND FILED THE SECURITIES AND SEPARATELY WITH EXCHANGE COMMISSION] THE SECURITIES AND EXCHANGE COMMISSION] Integrated Yield Management Services [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] Semiconductor Electrical Failure Analysis Services Price Per hour -------------- Capability (Unless otherwise stated) ---------- Device Analysis [CONFIDENTIAL INFORMATION OMITTED AND FILED [CONFIDENTIAL SEPARATELY WITH THE SECURITIES AND EXCHANGE INFORMATION OMITTED AND COMMISSION] FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION OMITTED AND FILED [CONFIDENTIAL SEPARATELY WITH THE SECURITIES AND EXCHANGE INFORMATION OMITTED AND COMMISSION] FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] Material Analysis [CONFIDENTIAL INFORMATION OMITTED AND FILED [CONFIDENTIAL SEPARATELY WITH THE SECURITIES AND EXCHANGE INFORMATION OMITTED AND COMMISSION] FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION OMITTED AND FILED [CONFIDENTIAL SEPARATELY WITH THE SECURITIES AND EXCHANGE INFORMATION OMITTED AND COMMISSION] FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION OMITTED AND FILED [CONFIDENTIAL SEPARATELY WITH THE SECURITIES AND EXCHANGE INFORMATION OMITTED AND COMMISSION] FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION OMITTED AND FILED [CONFIDENTIAL SEPARATELY WITH THE SECURITIES AND EXCHANGE INFORMATION OMITTED AND COMMISSION] FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION OMITTED AND FILED [CONFIDENTIAL SEPARATELY WITH THE SECURITIES AND EXCHANGE INFORMATION OMITTED AND COMMISSION] FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION OMITTED AND FILED [CONFIDENTIAL SEPARATELY WITH THE SECURITIES AND EXCHANGE INFORMATION OMITTED AND COMMISSION] FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] [CONFIDENTIAL INFORMATION OMITTED AND FILED [CONFIDENTIAL SEPARATELY WITH THE SECURITIES AND EXCHANGE INFORMATION OMITTED AND COMMISSION] FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] Priority processing: The standard charges above are for failure analysis completion within [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] of receipt by Fairchild. Expedited analysis (move to the top of the queue) is available at a [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] surcharge. The Parties agree that the minimum charge for failure analysis will be [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION] per job (any combination of service) or [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION], whichever is greater. Fairchild may accept National analysis work from other non-Fairchild wafer facilities, based on workload and analysis complexity. EXHIBIT K CYCLE TIME AND EXPEDITED PROCESSING HOT LOT CYCLE TIMES AND PRICING Fiscal Year 1998 Wafer Processing Cycle Times (in Days) Standard Hot Lot Super Hot Process cycle time cycle time cycle time - ------- ---------- ---------- ---------- West Jordan, Utah Fab: Standard Hot Lot Super Hot Process cycle time cycle time cycle time - ------- ---------- ---------- ---------- CE80 SLM 50 35 24 CE80 DLM 55 39 26 CS100P 50 35 24 CS100HE2 60 42 28 CS08OSG 48 34 23 CS08OSG3 60 42 25 CS65SE 60 42 24 South Portland, Maine Fab: Standard Hot Lot Super Hot Process cycle time cycle time cycle time ------- ---------- ---------- ---------- CS80C 42 29 23 CS80CBTX 52 36 28 CS80CBI 52 36 28 ABiC IV 2LM 58 44 36 ABiC IV 4LM 70 51 42 Interface Bipolar 27 19 15 Metal Gate CMOS 13 10 8 National will be charged a premium per hot lot started as follows: for Hot Lots, the premium will be $4,000. per lot for Super Hot Lots, the premium will be $10,000. per lot The standard lot sizes of 12 or 24 Wafers will apply. EXHIBIT L 1. Prices for Wafers manufactured in the six-inch fab in South Portland, Maine will be determined as follows. Shortly prior to the conclusion of the first six (6) fiscal periods under this Agreement ("Fiscal Half"), the Parties shall meet in order to determine new prices for the Second Fiscal Half. At that meeting the Parties will review the manufacturing history during such part of the First Fiscal Half for which such information shall be available in order to determine Fairchild's actual manufacturing cost base for that Wafer Module which shall be consistent with National's standard cost accounting practices in effect as of the Effective Date, (the "Class 1 Reference Cost Base"). If the Class 1 Reference Cost Base plus a twenty-five percent (25%) markup, is less than the price applicable for the first Fiscal Half, prices for the second Fiscal Half will be equal to the Class 1 Reference Cost Base plus a twenty-five percent (25%) markup. If Fairchild's actual costs have increased, the prices will remain the same. Exhibit N sets forth the prices for Wafers to be manufactured in the South Portland, Maine six-inch fab during the next twenty-seven (27) fiscal periods of this Agreement based on the forecast volumes. For different volumes, the prices may vary as set forth in the Revenue Side Letter. 2. Prices for Wafers manufactured on the four and five-inch fabs in South Portland, Maine and the West Jordan, Utah fab will be determined as follows. Shortly prior to the conclusion of the first Fiscal Half, the Parties shall meet in order to determine new prices for each of the aforementioned Wafer Modules for the second Fiscal Half. At that meeting the Parties will review the manufacturing history during such part of the first Fiscal Half for which such information shall be available in order to determine each Wafer Module's actual manufacturing cost base which shall be consistent with National's standard cost accounting practices in effect as of the Effective Date, (the "Reference Cost Base" per applicable Wafer Module). For each Wafer Module, if the Reference Cost Base plus a twenty-five percent (25%) markup is less than the price applicable for the first Fiscal Half, prices for the second Fiscal Half for that Wafer Module will be equal to its Reference Cost Base plus a twenty-five percent (25%) markup. If Fairchild's actual costs have increased, the prices for Wafers manufactured in that Wafer Module will remain the same as during the first Fiscal Half. The applicable Reference Cost Base and second Fiscal Half prices will remain in effect for each of the aforementioned Wafer Modules for the remaining term of this Agreement. Shortly prior to the conclusion of the eighteenth (18th) fiscal period of this Agreement, and every six (6) fiscal periods thereafter, the Parties shall meet in order to determine Fairchild's actual manufacturing costs for the preceding Fiscal Half which shall be consistent with National's standard cost accounting practices in effect as of the Effective Date. If a Wafer Module's actual costs during the previous Fiscal Half were lower than its Reference Cost Base, the Parties shall calculate what National would have paid if such actual costs had been used in originally setting the prices, rather than the applicable Reference Cost Base. Fairchild shall give National a credit equal to fifty percent (50%) of the savings National would have realized if it had paid the recalculated prices. No monies will be owing to or from National or to or from Fairchild if Fairchild's actual costs during the preceding Fiscal Half were higher than the applicable Reference Cost Base. 3. The prices for any Wafers or Equivalent Wafers purchased during a National fiscal year in excess of the Forecast Volumes are set forth in Exhibit N. 4. If National does not place orders for Wafers or Equivalent Wafers in accordance with the Forecast Volumes during any National fiscal year, the provisions of the Revenue Side Letter will apply with respect to the manner in which National will discharge its commitment to Fairchild for that fiscal year. 5. Pricing for any extension and/or ramp-down period beyond the first thirty-nine (39) fiscal periods of this Agreement will be negotiated in good faith by the Parties. Exhibit M 04-97 - ----- Water Equiv Equiv Fixed Starts Factor Wafers % of Feb Ovhd ------ ------ ------ -------- ---- CS080C 4.3 1.00 4.3 14.7% 1.9 CS80CBTX 9.6 1.27 12.2 41.7% 5.4 CS80C81 0.7 1.46 1.0 3.5% 0.5 ABIC 1.9 1.65 3.1 10.7% 1.4 Total NBC 15.5 20.6 70.6% 9.2 FSC 8.6 1.00 8.6 29.4% 3.8 Total 6" Fab 25. 29.2 100.0% 13.0 FY98 - ---- CS080C 24.6 1.00 24.6 24.6% 13.2 CS80CBTX 20.0 1.27 25.4 25.4% 13.6 CS80CBI 3.9 1.45 5.7 5.6% 3.0 ABIC 8.3 1.65 13.7 13.7% 7.3 Total NSC 56.8 69.4 69.2% 37.1 FSC 30.8 1.00 30.8 30.8% 16.5 Total 6" Fab 87.5 100.2 100.0% 53.6 FY99 - ---- Water Equiv Equiv Fixed Starts Factor Wafers % of Feb Ovhd ------ ------ ------ -------- ---- CS080C 0.0 1.00 0.0 0.05% 0.0 CS80CBTX 6.0 1.27 7.6 6.7% 3.6 CS80CBI 16.5 1.45 23.9 21.2% 11.4 ABIC 23.5 1.54 38.8 34.3% 18.4 Total NSC 46.0 70.3 62.3% 33.4 FSC 42.6 1.00 42.6 37.7% 20.2 Total 6" Fab 88.6 112.9 100.0% 53.6 FY00 - ---- Water Equiv Equiv Fixed Starts Factor Wafers % of Feb Ovhd ------ ------ ------ -------- ---- CS080C 0.0 1.00 0.0 0.0% 0.0 CS80CBTX 0.0 1.27 0.0 0.0% 0.0 CS80CBI 20.1 1.45 29.1 23.5% 12.6 ABIC 27.4 1.65 45.2 36.4% 19.5 Total NSC 47.5 74.4 59.9% 32.1 FSC 49.8 1.00 49.8 40.1% 21.5 Total 6" Fab 97.3 124.2 100.0% 53.6 Exhibit N -------------------------------------------------------------------------------------------------------- FY97 FY98 FY99 FY00 --------------------------------------------------------------------------------------------------- Q4 Q1 Q2 Q3 Q4 Year Q1 Q2 Q3 Q4 Year Q1 Q2 Q3 Q4 Year -------------------------------------------------------------------------------------------------------- South Portland - -------- Includes EPI where applicable ------ ------ ------ BCT1.0 Price 1,008 1,008 1,008 1,008 1,008 1,008 892 892 892 892 892 791 791 791 791 791 Starts 0.6 -- -- -- Revenue 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CS80C Price 1,008 1,008 1,008 1,008 1,008 1,008 892 892 892 892 892 791 791 791 791 791 Starts 3.7 6.4 5.9 6.4 5.9 24.6 -- -- Revenue 3.5 5.9 5.5 5.9 5.5 22.8 -- -- -- -- -- -- -- -- -- -- CS80CBTX Price 1,252 1,252 1,252 1,252 1,252 1,252 1,106 1,106 1,106 1,106 1,106 977 977 977 977 977 Starts 9.6 6.1 3.9 6.0 3.9 19.9 1.2 1.5 1.7 1.6 6.0 -- Revenue 10.8 6.9 4.4 6.8 4.4 22.4 1.2 1.5 1.7 1.6 6.0 -- -- -- -- -- CS809CBi Price 1,416 1,416 1,416 1,416 1,416 1,416 1,247 1,247 1,247 1,247 1,247 1,100 1,100 1,100 1,100 1,100 Starts 0.7 0.9 1.0 1.0 1.0 3.9 4.1 4.1 4.1 4.2 16.5 5.0 5.0 5.0 5.0 20.1 Revenue 0.9 1.1 1.3 1.3 1.3 5.0 4.6 4.6 4.6 4.7 18.5 5.0 5.0 5.0 5.0 19.9 ABiC 2LM Price 1,597 1,597 1,597 1,597 1,597 1,597 1,405 1,405 1,405 1,405 1,405 1,239 1,239 1,239 1,239 1,239 Starts 1.9 2.0 2.1 2.0 2.1 8.2 4.6 5.5 6.2 7.2 23.5 6.9 6.9 6.9 6.9 27.6 Revenue 2.7 2.8 3.0 2.8 3.0 11.7 5.8 6.9 7.8 9.0 29.4 7.6 7.6 7.6 7.6 30.4 ABiC 4LM Price 2,010 2,010 2,010 2,010 2,010 2,010 1,778 1,778 1,778 1,778 1,778 1,576 1,576 1,576 1,576 1,576 Starts 2.0 -- -- -- Revenue 0.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TOTAL Class 1 ASP 1,250 1,212 1,217 1,213 1,217 1,214 1,296 1,298 1,301 1,309 1,301 1,172 1,172 1,172 1,172 1,172 Starts 16.7 15.4 12.9 15.4 12.9 56.6 9.9 11.1 12.0 13.0 46.0 11.9 11.9 11.9 11.9 47.7 Revenue 18.8 16.8 14.1 16.8 14.1 61.9 11.5 13.0 14.0 15.3 53.9 12.6 12.6 12.6 12.6 50.3 Comm'l 4100 Price/4" 143 413 143 143 143 143 143 143 143 143 143 143 143 143 143 143 4" 36.5 36.5 36.5 36.5 36.5 145.9 30.9 30.9 30.9 30.9 123.7 26.2 26.2 26.2 26.2 104.7 Starts 6" equiv 16.2 16.2 16.2 16.2 16.2 64.8 13.7 13.7 13.7 13.7 55.0 11.6 11.6 11.6 11.6 46.5 Revenue 5.0 5.0 5.0 5.0 5.0 19.8 4.2 4.2 4.2 4.2 16.8 3.6 3.6 3.6 3.6 14.2 Comm'l 5100 Price/5" 222 222 222 222 222 222 222 222 222 222 222 222 222 222 222 222 5" 0.7 0.2 0.2 0.2 0.2 0.9 0.2 0.2 0.2 0.2 0.7 0.1 0.1 0.1 0.1 0.6 Starts 6" equiv 0.5 0.2 0.2 0.2 0.2 0.6 0.1 0.1 0.1 0.1 0.5 0.1 0.1 0.1 0.1 0.4 Revenue 0.1 0.0 0.0 0.0 0.0 0.2 0.0 0.0 0.0 0.0 0.2 0.0 0.0 0.0 0.0 0.1 Subtotal FM 6" 33.4 31.8 29.3 31.8 39.2 122.0 23.8 25.0 25.9 26.9 101.5 23.7 23.7 23.7 23.7 94.6 fabs Starts Revenue 23.9 21.8 19.1 21.8 19.1 81.9 15.8 17.2 18.3 19.5 70.8 16.2 16.2 16.2 16.2 64.7 TE-EPI Price 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 Starts 25.8 19.8 19.8 19.8 19.8 79.2 4.0 4.0 4.0 4.0 16.0 1.0 1.0 1.0 1.0 4.0 Revenue 1.2 0.9 0.9 0.9 0.9 3.6 0.2 0.2 0.2 0.2 0.7 0.0 0.0 0.0 0.0 0.2 ------ ------ ------ Exhibit N ----------------------------------------------------------------------------------------------------- FY97 FY98 FY99 FY00 ----------------------------------------------------------------------------------------------- Q4 Q1 Q2 Q3 Q4 Year Q1 Q2 Q3 Q4 Year Q1 Q2 Q3 Q4 Year ----------------------------------------------------------------------------------------------------- Salt Lake ------ ------ ------ CS100E2 Price 848 848 848 848 848 848 797 797 797 797 797 749 749 749 749 749 Starts 1.3 2.1 2.1 2.1 2.1 8.5 1.2 1.2 1.2 1.2 4.7 -- -- -- -- -- Revenue 1.0 1.7 1.7 1.7 1.7 6.6 0.9 0.9 0.9 0.9 3.5 -- -- -- -- -- CE130 Price 627 627 627 627 627 627 589 589 589 589 589 554 554 554 554 554 Starts 0.9 -- -- -- -- -- -- -- -- -- -- -- Revenue 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CE80 Price 669 669 669 669 669 669 628 628 628 628 628 591 591 591 591 591 Starts 1.3 2.4 2.4 2.4 2.4 9.6 0.6 0.6 0.6 0.6 2.2 -- -- -- -- -- Revenue 0.8 1.5 1.5 15. 1.5 1.5 5.9 0.3 0.3 0.3 1.3 -- -- -- -- -- CS80SG Price 1,789 1,789 1,789 1,789 1,789 1,789 1,682 1,682 1,682 1,682 1,682 1,581 1,581 1,581 1,581 1,581 Starts 0.1 0.1 0.1 0.1 0.1 0.4 -- -- -- -- -- -- -- -- -- -- Revenue 0.2 0.2 0.2 0.2 0.2 0.7 -- -- -- -- -- -- -- -- -- -- CS65 Price 2,141 2,141 2,141 2,141 2,141 2,141 2,013 2,013 2,013 2,013 2,013 1,892 1,892 1,892 1,892 1,892 Starts -- 0.3 0.3 0.3 0.3 1.0 0.0 0.0 0.0 0.0 0.1 -- -- -- -- -- Revenue -- 0.5 0.5 0.5 0.5 2.0 0.1 0.1 0.1 0.1 0.2 -- -- -- -- -- CE80DLM Price 755 755 755 7557 755 755 710 710 710 710 710 667 667 667 667 667 Starts Revenue TOTAL SL Revenue 773 864 864 864 864 864 782 782 782 782 782 n/a n/a n/a n/a n/a Starts 3.5 4.9 4.9 4.9 4.9 19.5 1.8 1.8 1.8 1.8 7.0 -- -- -- -- -- Revenue 2.4 3.8 3.8 3.8 3.8 15.2 1.2 1.2 1.2 1.2 5.0 -- -- -- -- -- ------ ------ ------ - -------------------------------------------------------------------------------- Prices for incremental volumes above the forecasted volumes will be priced per table: South Portland 4" commercial $ 70 5" commercial $110 6" fab ABiC2LM $825 CS80CBTX $635 CS80CBI $705 CS80C $500 BCT1.0 $705 ABiC4LM $1,000 - -------------------------------------------------------------------------------- EXHIBIT O PRINCIPLES OF MANUFACTURING (Degree) Forecasted volumes will be supplied covering all aspects of activity for 3 years. (Degree) National will meet a Revenue commitment of $330m over 3 years and 3 months, effective the day of closing of the purchase agreement. (Degree) Price will be fixed for the first 6 months. Pricing will reflect National's full absorption of the fixed cost based on its percent utilization of the South Portland, Maine 6" facility (i.e., this incorporates the agreed equivalency factors). (Degree) Principles will be set to establish pricing for the second 6 months. (Degree) Cost base for FM Class 1 will be Q4 Forecast FY97 with a fully capitalized base. (Degree) National will pay a mark up of 25% in the first 12 months. (Degree) For Class 1 the pricing after the initial 12 months is targeted to decline 12% or better given equal loadings in each subsequent interval. If the volume is greater price reduction will be increased accordingly. (Degree) Incremental volumes above the forecast volumes will be priced per table: 4" = $ 70 5" = $110 6" ABIC $825 CBTX $635 CBI $705 CS80 $500 (Degree) Available incremental capacity will be at the same rate as the base. (Degree) Pricing activity beyond Fiscal Year 00 - In case the Parties are unable to agree on prices for the following year, the prices used in the previous year will remain in effect, and the Parties will be allowed to reduce the capacity commitment each quarter by a quantity of 20%, starting one quarter after the price agreements expire. A notice shall be given 90 days prior to any capacity reduction. (Degree) For the Class 100 and the Penang Assembly and Test Facilities the price after the initial 12 months commitment will be at cost plus 25%. If the actual cost is better than the agreed upon base a credit will be given to National in the subsequent Fiscal Half equal to 50% of the savings. If the cost is greater than the agreed upon base, the price will be at the agreed upon base.