SECURITIES AND EXCHANGE COMMISSION
WASHINGTON, D.C 20549
FORM 10-K
COMMISSION FILE NUMBER: 0-18032
/ X / Annual report pursuant to Section 13 or 15(d) of the Securities
Exchange Act of 1934 for the fiscal year ended March 29, 1997 or
/ / Transition report pursuant to Section 13 or 15(d) of the Securities
Exchange Act of 1934 For the transition period from to
LATTICE SEMICONDUCTOR CORPORATION
(Exact name of Registrant as specified in its Charter)
DELAWARE 93-0835214
(State of Incorporation) (I.R.S Employer Identification No.)
5555 NE MOORE COURT, HILLSBORO, OREGON 97124-6421
(Address of principal executive offices) (Zip Code)
Registrant's telephone number, including area code: (503) 681-0118
SECURITIES REGISTERED PURSUANT TO SECTION 12(b) OF THE ACT: NONE
SECURITIES REGISTERED PURSUANT TO SECTION 12(g) OF THE ACT:
Title of Class Name of Exchange
Common Stock, $.01 par value NASDAQ
Preferred Share Purchase Rights None
Indicate by check mark whether the Registrant (1) has filed all reports
required to be filed by Section 13 or 15(d) of the Securities Exchange Act of
1934 during the preceding 12 months (or for such shorter period that the
Registrant was required to file such reports), and (2) has been subject to
such filing requirements for the past 90 days.
Yes X No
----- -----
Indicate by check mark if disclosure of delinquent filers pursuant to
Item 405 of Regulation S-K is not contained herein, and will not be
contained, to the best of the Registrant's knowledge, in definitive proxy or
information statements incorporated by reference in Part III of this Form
10-K or any amendment to this Form 10-K.
Yes No X
----- -----
As of June 12, 1997, the aggregate market value of the shares of voting
stock of the Registrant held by non-affiliates was approximately $785
million. Shares of Common Stock held by each officer and director and by each
person who owns 5% or more of the outstanding Common Stock have been excluded
in that such persons may be deemed affiliates. This determination of affiliate
status is not necessarily a conclusive determination for other purposes.
As of June 12, 1997, 23,066,825 shares of the Registrant's common stock
were outstanding.
DOCUMENTS INCORPORATED BY REFERENCE
1. Portions of the Annual Report to Stockholders for the fiscal year
ended March 29, 1997 are incorporated by reference in Part II hereof.
2. Portions of the definitive proxy statement of the Registrant to be
filed pursuant to Regulation 14A for the 1997 Annual Meeting of Stockholders
to be held on August 11, 1997 are incorporated by reference in Part III
hereof.
LATTICE SEMICONDUCTOR CORPORATION
FORM 10-K
ANNUAL REPORT
TABLE OF CONTENTS
Item of Form 10-K Page
- - - ----------------- ----
PART I
Item 1 - Business . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Item 2 - Properties . . . . . . . . . . . . . . . . . . . . . . . . . 16
Item 3 - Legal Proceedings . . . . . . . . . . . . . . . . . . . . . 17
Item 4 - Submission of Matters to a Vote of Security Holders . . . . 17
Item 4(a) - Executive Officers of the Registrant . . . . . . . . . . . . 18
PART II
Item 5 - Market for the Registrant's Common Stock and Related
Stockholder Matters . . . . . . . . . . . . . . . . . . . . 20
Item 6 - Selected Financial Data . . . . . . . . . . . . . . . . . . 20
Item 7 - Management's Discussion and Analysis of Financial Condition
and Results of Operations . . . . . . . . . . . . . . . . . 21
Item 8 - Financial Statements and Supplementary Data . . . . . . . . 21
Item 9 - Changes in and Disagreements with Accountants on Accounting
and Financial Disclosure . . . . . . . . . . . . . . . . . 21
PART III
Item 10 - Directors and Executive Officers of the Registrant . . . . . 22
Item 11 - Executive Compensation . . . . . . . . . . . . . . . . . . . 22
Item 12 - Security Ownership of Certain Beneficial Owners and
Management . . . . . . . . . . . . . . . . . . . . . . . . 22
Item 13 - Certain Relationships and Related Transactions . . . . . . . 22
PART IV
Item 14 - Exhibits, Financial Statement Schedules and Reports on
Form 8-K . . . . . . . . . . . . . . . . . . . . . . . . . 23
Signatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Financial Statement Schedules . . . . . . . . . . . . . . . . . . . . . . . S-1
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BUSINESS
This Report contains forward-looking statements within the meaning of Section
27A of the Securities Act of 1933, as amended, and Section 21E of the
Securities Exchange Act of 1934, as amended. Actual results could differ
materially from those projected in the forward-looking statements as a result
of the factors set forth in "Factors Affecting Future Results" and elsewhere
in this Report.
GENERAL
Lattice Semiconductor Corporation (the "Company") designs, develops and
markets high performance programmable logic devices ("PLDs") and related
development system software. The Company is the inventor and world's leading
supplier of in-system programmable ("ISP-TM-") PLDs. PLDs are standard
semiconductor components that can be configured by the end customer as
specific logic functions, enabling shorter design cycle times and reduced
development costs. Lattice was founded in 1983 and is based in Hillsboro,
Oregon.
PLD MARKET BACKGROUND
Three principal types of digital integrated circuits are used in most
electronic systems: microprocessors, memory and logic. Microprocessors are
used for control and computing tasks, memory is used to store programming
instructions and data, and logic is employed to manage the interchange and
manipulation of digital signals within a system. Logic contains
interconnected groupings of simple logical "AND" and logical "OR" functions,
commonly described as "gates". Typically, complex combinations of individual
gates are required to implement the specialized logic functions required for
systems applications. While system designers use a relatively small number of
standard architectures to meet their microprocessor and memory needs, they
require a wide variety of logic circuits in order to achieve end product
differentiation.
Logic circuits are found in a wide range of today's electronic systems
including communications equipment, computers, peripherals, instrumentation,
industrial controls and military systems. According to Dataquest
Incorporated, a semiconductor market research firm, logic accounted for
approximately 31% of the estimated $103 billion worldwide digital integrated
circuit market in 1996. The logic market encompasses, among other segments,
standard logic, custom-designed application specific integrated circuits
("ASICs", which include conventional gate-arrays, standard cells and full
custom logic circuits), and PLDs. Logic is often classified by the number of
gates per chip, with PLDs offering up to 50,000 gates, and conventional gate
arrays and custom logic circuits reaching up to several hundred thousand
gates.
Manufacturers of electronic systems are increasingly challenged to bring
differentiated products to market quickly. These competitive pressures often
preclude the use of custom-designed ASICs, which generally entail significant
design risks and time delay. Standard logic products, an alternative to
custom-designed ASICs, limit a manufacturer's flexibility to adequately
customize an end system. Programmable logic addresses this inherent dilemma.
PLDs are standard products, purchased by systems manufacturers in a "blank"
state, that can be
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custom configured into a virtually unlimited number of specific logic
functions by programming the device with electrical signals. PLDs give system
designers the ability to quickly create their own custom logic functions to
provide product differentiation without sacraficing rapid time to market.
Certain PLD products, including the Company's, are reprogrammable, meaning
that the logic configuration can be modified, if needed, after the initial
programming. A recent development pioneered by the Company, in-system
programmable PLDs, extends the flexibility of standard reprogrammable PLDs by
allowing the system designer to configure and reconfigure the logic functions
of the PLD with standard 5-volt or 3.3-volt power supplies without removing
the PLD from the system board.
Several common types of PLDs currently coexist in the marketplace, each
offering customers a particular set of benefits. These include low-density
PLDs (less than 1,000 gates) and high-density PLDs (greater than 1,000
gates). High-density PLDs include both complex PLDs ("CPLDs," up to 25,000
gates) and field programmable gate arrays ("FPGAs," up to 50,000 gates).
Low-density devices are typically based on industry standard architectures
and include the GAL-Registered Trademark- ("Generic Array Logic") product
family developed by the Company. These architectures are familiar to most
system designers and are supported by standard widely available development
tools. Offering the highest absolute performance and lowest cost per device,
these products are the most effective PLD solution to support simple logic
functions.
High-density devices are typically based on proprietary architectures and
require support from sophisticated computer aided engineering ("CAE")
development tools. Due to higher levels of logic integration, absolute
performance typically lags that of state-of-the-art low-density PLDs by one
or more technology generations. However, in situations requiring complex
logic functions, high-density PLDs can provide important advantages over
a large cluster of low-density devices. These advantages include system
performance enhancement and power and cost savings.
CPLDs and FPGAs are the two primary types of high-density PLD architectures.
Each architecture is generally optimal for different types of logic
functions, although many logic functions can be implemented with either
architecture. CPLDs are characterized by a regular building block structure
of wide-input logic cells, termed macrocells, and use of a centralized logic
interconnect scheme. CPLDs are optimal for control logic applications, such
as state machines, bus arbitration, encoders, decoders and sequencers. FPGAs
are characterized by a narrow-input logic cell and use a distributed
interconnect scheme. FPGAs are optimal for register intensive and data path
logic applications such as interface logic and arithmetic functions. The
Company believes that a substantial portion of high-density PLD customers
utilize both CPLD and FPGA architectures within a single system design,
partitioning logic functions across multiple devices to optimize overall
system performance and cost.
TECHNOLOGY
The Company believes that electrically erasable CMOS ("E(2)CMOS-Registered
Trademark-") is the preferred process technology for both high-density CPLDs
and low-density PLDs due to its inherent performance, reprogrammability and
testability benefits. E(2)CMOS, through its fundamental ability to be
programmed and erased electronically, serves as the foundation for the
Company's ISP products.
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IN-SYSTEM PROGRAMMABLE (ISP) PRODUCTS AND TECHNOLOGY
The Company has pioneered the development of ISP products, based on a
proprietary technology, which affords it a competitive advantage in the
high-density CPLD market. In contrast to standard PLDs, ISP devices can be
configured and reconfigured by the system designer without being removed from
the printed circuit board. Standard E(2)CMOS programmable logic devices require
12-volt electrical signals and therefore must be removed from the printed
circuit board and programmed using stand alone, specialized hardware, while
ISP devices can be programmed with standard 5-volt or 3.3-volt electrical
signals. ISP devices offer enhanced flexibility versus standard PLDs,
providing a number of important benefits to a system manufacturer across the
full spectrum of an electronic system product cycle. ISP devices can allow
customers to reduce design cycle times, accelerate time to market, reduce
prototyping costs, reduce manufacturing costs and lower inventory
requirements. ISP devices can also provide customers the opportunity to
perform simplified and cost-effective field reconfiguration through a data
file transferred by computer disk or serial data signal. All of the Company's
high-density CPLDs are available with ISP. The Company also offers its most
popular low-density architecture, the GAL22V10, with ISP.
E(2)CMOS PROCESS TECHNOLOGY
The Company's current high- and low-density PLD offerings are based on the
Company's proprietary E(2)CMOS manufacturing process technology, termed
UltraMOS-Registered Trademark-. The Company's current production processes,
UltraMOS IV, UltraMOS V and UltraMOS VI are sub-micron CMOS technologies.
In comparison to bipolar technology, at one time the dominant technology for
low-density PLDs, E(2)CMOS technology consumes less power and generates less
heat while operating at comparable speed. Additionally, in contrast to
one-time-programmable bipolar PLDs, E(2)CMOS PLDs are fully erasable and
reprogrammable, providing greater end customer design flexibility and
allowing the PLD manufacturer to fully test all programmable elements in a
device prior to shipment. An alternative CMOS technology, Erasable
Programmable Read Only Memory ("EPROM"), provides the same low power
consumption benefits as E(2)CMOS, but requires ultraviolet light exposure for
erasure, necessitating expensive quartz windowed packages and limiting
testability. Antifuse and Static Random Access Memory ("SRAM") technologies,
used primarily in the manufacture of high-density FPGAs, offer certain
advantages for very dense logic devices, but also have significant drawbacks
when compared with E(2)CMOS. Antifuse technology is non-erasable,
non-reprogrammable and subject to lengthy initial programming times that can
hinder usage in volume production applications. SRAM technology is volatile
(erases when electrical power is removed), and as such programmable SRAM
FPGAs require additional non-volatile memory, typically on a separate device,
to store programming code. This adds cost and printed circuit board area to a
design, and results in the devices not being completely functional at initial
system power-up.
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PRODUCTS
HIGH-DENSITY CPLDS
SILICON. The Company first entered the high-density market in fiscal 1993
and currently offers four distinct families of ispLSI-Registered
Trademark-products, each consisting of multiple devices. All devices are
offered with ISP. The Company is currently shipping over 125 speed, package
and temperature range combinations of high-density CPLDs.
ISPLSI 1000/E: The Company's original high-density family utilizes an
innovative, proprietary architecture incorporating familiar GAL-like logic
building blocks. This family offers performance of up to 125 MHz, with
propagation delays as low as 7.5 nanoseconds, densities of 2,000 to 8,000
gates, and is available in surface mount packages ranging from 44- to
128-pins.
ISPLSI 2000/V: The ispLSI 2000 family utilizes an architecture designed for
input/output ("I/O") intensive applications and offers industry leading CPLD
performance. This family provides performance of up to 180 MHz, with
propagation delays as low as 5 nanoseconds, densities of 1,000 to 6,000
gates, and 44- to 176-pin standard surface mount packages. The ispLSI 2000LV
family, an extension of the ispLSI 2000 family, operates using the emerging
3.3-volt power supply standard. Offered with a range of density, performance
and package specifications, the ispLSI 2000LV family is targeted towards
emerging high-growth, low-voltage system applications in the computing and
communication markets.
ISPLSI 3000: The ispLSI 3000 family incorporates an enhanced logic
architecture to target higher density applications while retaining high
performance. It offers densities of 7,000 to 14,000 gates, and performance
of up to 125 MHz, with propagation delays as low as 7.5 nanoseconds.
Available in 160- to 304-pin surface mount packages, the 3000 family also
incorporates boundary scan test, an attractive feature that provides enhanced
testing capabilities important for complex systems.
ISPLSI 6000: The ispLSI 6000 family extends the Company's high-density CPLD
density range to 25,000 gates. This family utilizes an innovative cell-based
architecture that combines a general purpose high-density CPLD with memory
and other function specific circuit blocks. Offered with performance of up
to 77 MHz, with propagation delays as low as 15 nanoseconds, the ispLSI 6000
family allows integration of complete logic subsystems in the communications,
computing and multimedia markets.
The Company plans to continue to introduce new families of high-density
products, as well as improve the performance of existing product families, to
meet market needs.
SOFTWARE DEVELOPMENT TOOLS. All of the Company's high-density products are
supported by the Company's ispDS-TM- software development tools and
ispDS+-TM- software development tools (referred to as "fitters"). Designed to
be a low cost, fully integrated development tool, ispDS runs under the
Microsoft Windows operating system on a personal computer. ispDS software
allows a customer to enter and verify a logic design, perform logic
minimization, assign I/O pins and critical speed paths, simulate timing,
execute automatic place and route tasks and download a program to an ISP
device. Designed to provide a seamless integration of the Company's
development tools with standard design environments, ispDS+ software
leverages customers' existing investments in third-party CAE tools.
Optimized for HDL synthesis, ispDS+ software supports all
5
popular third party CAE development tool environments running on IBM
compatible personal computers as well as workstations from Sun Microsystems
and Hewlett-Packard. The Company offers ispDS+ products supporting common
third party CAE design tool environments, including Cadence, Data I/O ABEL,
Data I/O Synario, Exemplar, Isdata, Logical Devices, Mentor Graphics, OrCAD,
Synopsys, Synplicity and ViewLogic. ispDS+ software allows a customer to
compile a design developed in a third party environment, assign I/O pins and
critical speed paths, simulate and analyze timing, execute automatic place
and route tasks and download a program to an ISP device. In fiscal 1997, the
Company released new versions of its existing ispDS and ispDS+ software
development tools to enhance performance, functionality and ease of use.
The Company also provides several software algorithms that support in-system
programming of the Company's ISP devices. These software products include
ispCODE-TM-, ispDOWNLOAD-TM-, ispREMOTE-TM- and ispATE-TM-. ispATE enables
ISP product programming to be integrated into automatic test equipment
("ATE") on the manufacturing floor.
During fiscal 1997, the number of installed seats of the Company's software
development tools, as measured by the Company, grew from over 10,000 to over
17,000. The Company plans to continue to enhance and expand its development
tool offerings.
LOW-DENSITY PLDS
The Company offers the industry's broadest line of low-density CMOS PLDs
based on its 16 families of GAL products offered in over 200 speed, power,
package and temperature range combinations. GAL devices range in complexity
from approximately 200 to 1,000 logic gates and are typically assembled in
20-, 24-and 28-pin standard dual in-line packages and in 20- and 28-pin
standard plastic leaded chip carrier packages. The Company offers the
industry standard GAL16V8, GAL20V8, GAL22V10, GAL20RA10 and GAL20XV10
architectures in a variety of speed grades, with propagation delays as low as
3.5 nanoseconds, the highest performance in the industry. The Company also
offers several innovative proprietary extension architectures, the
ispGAL-Registered Trademark-22V10, GAL26CV12, GAL18V10, GAL16VP8, GAL20VP8,
GAL6001/2, GAL16V8Z and GAL20V8Z, each of which is optimized for specific
applications. These product families offer industry leading performance
levels, typically with propagation delays as low as 7.5 nanoseconds. The
Company extended its GAL line by introducing a family of 3.3-volt industry
standard architectures, the GAL16LV8, GAL20LV8, GAL22LV10 and GAL26CLV12 in a
variety of speed grades, with propagation delays as low as 3.5 nanoseconds,
the highest performance in the industry. Offered with a range of power
consumption specifications, these devices are targeted towards emerging
high-growth, low-voltage system applications in the communication and
computing markets. The Company is currently selling the GAL16LV8D-3.5, the
world's fastest PLD available in any technology or operating voltage.
The Company plans to continue to maintain a broad offering of performance
leadership, standard and proprietary architecture low-density CMOS PLDs.
The Company's GAL products are supported by industry standard software and
hardware development tools marketed by independent manufacturers specifically
for PLD applications.
6
PRODUCT DEVELOPMENT
The Company places great emphasis on product development and believes that
continued investment in the development of new products that exploit market
trends is required to maintain its competitive position. The Company's
product development activities emphasize new high-density PLDs, improvements
of its proprietary ISP products and E(2)CMOS processes technologies,
performance enhancement and cost reduction of existing products, and
extension and enhancement of its software development tools. Product
development activities occur in the Company's Hillsboro, Oregon headquarters,
its Milpitas, California product development center, and its Shanghai, China
design center.
Research and development expenses were $22.9 million, $26.8 million and $27.8
million in fiscal years 1995, 1996 and 1997, respectively. The Company
expects to continue to make significant investments in research and
development in the future.
OPERATIONS
The Company does not manufacture its silicon wafers. The Company has
historically maintained strategic relationships with large semiconductor
manufacturers in order to source its finished silicon wafers, allowing the
Company to focus its internal resources on product, process and market
development. In addition, assembly is performed for the Company by outside
suppliers. The Company performs most test operations and reliability and
quality assurance processes internally, as the Company believes it can add
significant customer value in these areas. The Company has achieved ISO 9001
quality certification, an indication of the Company's high internal
operational standards.
WAFER FABRICATION
The majority of the Company's silicon wafer requirements are currently
supplied by Seiko Epson Corporation ("Seiko Epson") in Japan pursuant to an
agreement with S MOS Systems, Inc. ("S MOS"), an affiliated U.S. distributor
of Seiko Epson. See "Licenses and Agreements - Seiko Epson/S MOS." The
Company negotiates wafer volumes, prices and terms with Seiko Epson and S MOS
on a periodic basis. In addition, the Company receives silicon wafers from
United Microelectronics Corporation ("UMC") in Taiwan pursuant to an
agreement entered into in 1995. Wafer prices and other purchase terms related
to this commitment are subject to periodic adjustment. See " Licenses and
Agreements - UMC." A significant interruption in supply from Seiko Epson
through S MOS or from UMC would have a material adverse effect on the
Company's business. See "Factors Affecting Future Results."
7
ASSEMBLY
After wafer fabrication and initial testing, the Company ships wafers to
independent subcontractors for assembly. During assembly, wafers are
separated into individual die and encapsulated in plastic or ceramic
packages. Presently, the Company has qualified long-term assembly partners in
Hong Kong, Malaysia, the Philippines, South Korea and the United States.
TESTING
The Company electrically tests the die on each wafer prior to shipment for
assembly. Following assembly, prior to customer shipment, each product
undergoes final testing using test equipment, techniques and quality
assurance procedures. Final testing on certain products is performed at
independent contractors in Malaysia, the Philippines, South Korea and the
United States.
MARKETING, SALES AND CUSTOMERS
The Company sells its products directly to end customers through a network of
independent sales representatives and indirectly through a network of
distributors. The Company utilizes a direct sales management and field
applications engineering organization in combination with manufacturers'
representatives and distributors to reach a broad base of potential end
customers. The Company's end customers are primarily original equipment
manufacturers in the fields of communications, computing, peripherals,
instrumentation, industrial controls and military systems. The Company
believes its distribution channel is a cost-effective means of reaching end
customers.
At March 29, 1997, the Company had 19 sales representatives and five
distributors in the United States and Canada. In North America, Arrow
Electronics, Inc., Hamilton Hallmark, Insight Electronics, Inc. and Marshall
Industries provide nationwide distribution, while Future Electronics provides
regional distribution coverage in Canada. The Company has established sales
channels in over 30 foreign countries through a network of over 30 sales
representatives and distributors. Approximately one-half of the Company's
North American sales and most of its foreign sales are made through
distributors.
The Company protects each of its North American distributors and some of its
foreign distributors against reductions in published prices, and expects to
continue this policy in the foreseeable future. The Company also allows
returns from these distributors of unsold products under certain conditions.
For these reasons, the Company does not recognize revenue until products are
resold by these distributors.
The Company provides technical and marketing assistance to its end customers
and sales force with engineering staff based in the Company's headquarters,
design centers and selected field sales offices. The Company maintains 21
domestic and international sales offices where the Company's field sales
managers and applications engineers are based. These offices are located in
the metropolitan areas of Atlanta, Austin, Boston, Chicago, Dallas, Denver,
Los Angeles, Minneapolis, Orlando, Portland, Raleigh, San Diego, San Jose,
Hong Kong, London, Munich, Paris, Seoul, Stockholm, Taipei and Tokyo.
International revenues, including those from Canada, accounted for 47%, 48%
and 49% of the Company's revenues in fiscal 1995, 1996 and 1997, respectively.
Revenues from Europe were $24.5 million, $37.9 million
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and $ 39.9 million, and from Asia were $40.6 million, $52.4 million and $
52.6 million, in fiscal 1995, 1996 and 1997, respectively. Both international
and domestic revenues are generally invoiced in U.S. dollars with the
exception of sales in Japan which are invoiced in yen.
The Company's products are sold to a large and diverse group of customers. No
individual end customer accounted for more than 5% of revenue in either fiscal
1995, 1996 or 1997. Two distributors accounted for approximately 12% and
11% of revenue in fiscal 1995. One distributor accounted for approximately
11% of revenue in fiscal 1996. No distributor accounted for more than 10% of
revenue in fiscal 1997.
The Company's sales are primarily executed against purchase orders for
standard products. Customers frequently revise quantities and delivery
schedules, without penalty. The Company therefore does not believe that
backlog as of any given date is indicative of future revenue.
COMPETITION
The semiconductor industry overall is intensely competitive and is
characterized by rapid technological change, rapid rates of product
obsolescence and price erosion. The Company's current and potential
competitors include a broad range of semiconductor companies, ranging from
very large, established companies to emerging companies, many of which have
greater financial, technical, manufacturing, marketing and sales resources
than the Company.
The principal competitive factors in the CMOS PLD market include product
features, price, customer support, and sales, marketing and distribution
strength. In the high-density segment, the availability of competitive
software development tools is also critical. In addition to product features
such as speed, power consumption, reprogrammability, design flexibility and
reliability, competition in the PLD market occurs on the basis of price and
market acceptance of specific products and technology. The Company believes
that it competes favorably with respect to each of these factors. The Company
intends to continue to address these competitive factors by working to
continually introduce product enhancements and new products, by seeking to
establish its products as industry standards in their respective markets, and
by working to reduce the manufacturing cost of its products over their life
cycle.
In the high-density PLD market, the Company primarily competes directly with
Advanced Micro Devices ("AMD") and Altera, both of which offer competing CPLD
products. The Company also competes indirectly with manufacturers of FPGA
devices such as Actel, Lucent, and Xilinx as well as other semiconductor
companies providing non-PLD based logic solutions. As the Company and these
other companies seek to expand their markets, competition may increase.
In the low-density PLD market, the Company competes primarily with AMD, a
licensee of the Company's GAL patents, which offers a full line of E(2)CMOS
GAL-compatible PLDs. Altera, Atmel and Cypress Semiconductor offer products
based on similar and competing CMOS technologies and architectures, however,
these companies do not offer full product lines.
Although to date the Company has not experienced significant competition from
companies located outside the United States, such companies may become a more
significant competitive factor in the future. As the
9
Company and its current competitors seek to expand their markets, competition
may increase. Any such increases in competition could have a material adverse
effect on the Company's operating results.
PATENTS
The Company seeks to protect its products and wafer fabrication process
technology primarily through patents, trade secrecy measures, copyrights,
mask work protection, trademark registrations, licensing restrictions,
confidentiality agreements and other approaches designed to protect
proprietary information. There can be no assurance that others may not
independently develop competitive technology not covered by the Company's
patents or that measures taken by the Company to protect its technology will
be effective.
The Company holds domestic, European and Japanese patents on its PLD
products and has patent applications pending in the United States, Japan and
under the European Patent Convention. There can be no assurance that pending
patent applications or other applications that may be filed will result in
issued patents, or that any issued patents will survive challenges to their
validity. Although the Company believes that its patents have value, there
can be no assurance that the Company's patents, or any additional patents
that may be issued in the future, will provide meaningful protection from
competition. The Company believes its success will depend primarily upon the
technical expertise, experience, creativity and the sales and marketing
abilities of its personnel.
Patent and other proprietary rights infringement claims are common in the
semiconductor industry. The Company has received a letter from a
semiconductor manufacturer stating that it believes a number of its patents,
related to product packaging, cover certain products sold by the Company.
While the manufacturer has offered to license certain of such patents to the
Company, there can be no assurance, on this or any other claim which may be
made against the Company, that the Company could obtain a license on terms or
under conditions that would be favorable to the Company.
LICENSES AND AGREEMENTS
SEIKO EPSON/S MOS
S MOS, an affiliated U.S. distributor of Seiko Epson, has agreed to provide
manufactured wafers to the Company in quantities based on six-month rolling
forecasts provided by the Company. The Company has committed to buy certain
minimum quantities of wafers per month. The Company's products are
manufactured in Japan at Seiko Epson's wafer fabrication facilities and
delivered to the Company by S MOS. Prices for the wafers obtained from S MOS
are reviewed and adjusted periodically and may be adjusted to reflect
prevailing currency exchange rates. See "Factors Affecting Future Results."
Daniel S. Hauer, a member of the Company's Board of Directors, is Chairman of
the Board of Directors of S MOS.
In July 1994, the Company entered into an advance production payment
agreement with Seiko Epson and S MOS, under which it advanced to Seiko Epson
$42 million during fiscal 1995 to be used by Seiko Epson to finance
additional sub-micron semiconductor wafer manufacturing capacity. Under the
terms of the agreement, the advance is to be repaid in the form of advanced
technology sub-micron semiconductor wafers. Subject to certain conditions set
forth in the agreement, Seiko Epson has agreed to supply, and the Company has
agreed to receive, such wafers at a price (in Japanese yen) and volume
expected to achieve full repayment of the advance
10
over a three- to four-year period. In conjunction with the advance production
payment agreement, the Company also paid $2 million during fiscal 1995 for
the development of sub-micron process technology and the fabrication of
engineering wafers to be delivered over the same period. The agreement calls
for wafers to be supplied by Seiko Epson through S MOS pursuant to a purchase
agreement concluded with S MOS. Total wafer receipts under these agreements
aggregated approximately $30.2 million as of March 29, 1997.
In March 1997, the Company entered into a second advance production payment
agreement with Seiko Epson and SMOS under which it agreed to advance
approximately $90 million, payable over two years, to Seiko Epson to finance
construction of an eight-inch sub-micron semiconductor wafer manufacturing
facility. The timing of the payments is related to certain milestones in the
development of the facility. Under the terms of the agreement, the advance
is to be repaid with semiconductor wafers over a multi-year period. The
agreement calls for wafers to be supplied by Seiko Epson through S MOS
pursuant to purchase agreements concluded with S MOS. The Company also has
an option under the agreement to advance Seiko Epson an additional $60
million for additonal wafer supply under similar terms. The first payment
pursuant to this agreement, approximately $17.0 million, was made during March
1997.
UMC
The Company entered into a series of agreements with UMC in September 1995
pursuant to which the Company agreed to join UMC and several other companies
to form a separate Taiwanese company, UICC, for the purpose of building and
operating an advanced semiconductor manufacturing facility in Taiwan,
Republic of China. Under the terms of the agreement, the Company will invest
approximately $53 million, payable in three installments, for a 10% equity
interest in UICC and the right to receive a percentage of the facility's
wafer production at market prices. The timing of the payments is related to
certain milestones in the development of the advanced semiconductor
manufacturing facility. The first payment, in the amount of $13.7 million,
was paid in January 1996, the second payment, in the amount of approximately
$25.8 million, was paid during January 1997, and the final payment is
anticipated to be required within the six-month period ending December 1997.
AMD
In November 1987, as part of the settlement of a patent infringement suit
against the Company, the Company and Monolithic Memories, Inc. ("MMI",
subsequently merged with AMD) entered into an agreement cross-licensing each
other's patents covering programmable and reprogrammable logic devices based
on patent applications having a first filing date prior to November 1989. The
agreement was subsequently amended in May 1989 by the Company and AMD, the
successor to the rights and obligations of MMI in the original agreement. The
amendment covers those patents relating to PLD products which are based on
patent applications originally filed by the Company, MMI and AMD prior to
December 31, 1991. The license terminates, with respect to certain patents
asserted by AMD, to cover the Company's current principal products if the
Company is acquired by a semiconductor manufacturer with sales in excess of a
stated amount or by certain types of companies headquartered in designated
Asian countries. No license has been granted to either party for any
copyright work, trademark or process technology and, therefore, AMD has not
been licensed to use the GAL trademark on its products.
11
FACTORS AFFECTING FUTURE RESULTS
The Company believes that its future operating results will be subject to
quarterly variations based upon a wide variety of factors, including the
cyclical nature of both the semiconductor industry and the end markets
addressed by the Company's products, the timing of new product introductions,
price erosion, product obsolescence, substantial adverse currency exchange
rate movements, variations in product mix, scheduling, rescheduling and
cancellation of large orders, competitive factors, the availability of
manufacturing capacity and wafer supply, the ability to achieve volume
production at Seiko Epson's new eight-inch facility or UICC, the ability to
develop and implement new process technologies, fluctuations in manufacturing
yields, changes in effective tax rates and litigation expenses. Due to these
and other factors, the Company's past results are a less useful predictor of
future results than is the case in more mature and stable industries. The
Company has increased its level of operating expenses and investment in
manufacturing capacity in anticipation of future growth in revenues,
primarily from increased sales of its high-density products. To the extent
that this revenue growth does not materialize, the Company's operating
results would be adversely affected.
The semiconductor industry is highly cyclical and has been subject to
significant downturns at various times that have been characterized by
diminished product demand, production overcapacity and accelerated erosion of
average selling prices. The Company's rate of growth in recent periods has
been positively and negatively impacted by trends in the semiconductor
industry. Any material imbalance in industry-wide production capacity
relative to demand, shift in industry capacity toward products competitive
with the Company's products, reduced demand or reduced growth in demand or
other factors could result in a decline in the demand for or the prices of
the Company's products and could have a material adverse effect on the
Company's operating results.
The market price of the Company's common stock could be subject to
significant fluctuations in response to variations in quarterly operating
results, shortfalls in revenues or earnings from levels expected by
securities analysts and other factors such as announcements of technological
innovations or new products by the Company or by the Company's competitors,
government regulations, developments in patent or other proprietary rights,
and developments in the Company's relationships with parties to collaborative
agreements. In addition, the stock market can experience significant price
fluctuations. These fluctuations often are unrelated to the operating
performance of the specific companies whose stocks are traded. Broad market
fluctuations, as well as economic conditions generally and in the
semiconductor industry specifically, could adversely affect the market price
of the Company's common stock.
The Company does not manufacture finished silicon wafers. Its products,
however, require wafers manufactured with state-of-the-art fabrication
equipment and techniques. Accordingly, the Company's strategy has been to
maintain relationships with large semiconductor manufacturers for the
production of its wafers. Currently all of its silicon wafers are
manufactured by either Seiko Epson in Japan or UMC in Taiwan. A significant
interruption in supply from Seiko Epson, through S MOS, Seiko Epson's
affiliated U.S. distributor, or from UMC would have a material adverse effect
on the Company's business.
Worldwide manufacturing capacity for silicon wafers is limited and inelastic.
Therefore, significant increases in demand or interruptions in supply could
adversely affect the Company. Through fiscal 1997, the Company was
successful in obtaining adequate wafer capacity commitments; however, it has
in the past experienced delays in obtaining wafers. Although current
commitments are anticipated to be adequate through fiscal 1998, there can be
12
no assurance that existing capacity commitments will be sufficient to permit
the Company to satisfy all of its customers' demand in future periods. The
Company negotiates wafer prices and certain wafer supply commitments with
Seiko Epson, S MOS and UMC on an annual basis, and, in some cases, as
frequently as semiannually. Moreover, wafer prices and commitments are
subject to continuing review and revision by the parties. There can be no
assurance that Seiko Epson, S MOS or UMC will not reduce their allocations of
wafers or increase prices to the Company in future periods or that any such
reduction in supply could be offset pursuant to arrangements with alternate
sources of supply. If any substantial reduction of supply or substantial
price increase were to occur, the Company's operating results could be
materially adversely affected.
The Company's wafer purchases from Seiko Epson are denominated in Japanese
yen. In the past, the dollar has lost substantial value with respect to the
yen. There is no assurance that the value of the dollar with respect to the
yen will not again experience substantial deterioration. Any substantial
continued deterioration of dollar-yen exchange rates could have a material
adverse effect on the Company's results of operations.
The Company depends upon wafer suppliers to produce wafers with acceptable
yields and to deliver them to the Company in a timely manner. Substantially
all of the Company's revenues are derived from products based on E(2)CMOS
process technology. Successful implementation of the Company's proprietary
E(2)CMOS process technology, UltraMOS, requires a high degree of coordination
between the Company and its wafer supplier. Therefore, significant lead time
is required to reach volume production at a new wafer supply location such as
Seiko Epson's new eight-inch facility or UICC. Accordingly, there can be no
assurance that volume production at Seiko Epson's new eight-inch facility or
UICC will be achieved in the near term or at all. The manufacture of high
performance E(2)CMOS semiconductor wafers is a complex process that requires a
high degree of technical skill, state-of-the-art equipment and effective
cooperation between the wafer supplier and the circuit designer to produce
acceptable yields. Minute impurities, errors in any step of the fabrication
process, defects in the masks used to print circuits on a wafer and other
factors can cause a substantial percentage of wafers to be rejected or
numerous die on each wafer to be non-functional. As is common in the
semiconductor industry, the Company has from time to time experienced in the
past, and expects that it will experience in the future, production yield
problems and delivery delays. Any prolonged inability to obtain adequate
yields or deliveries could adversely affect the Company's operating results.
The Company expects that, as is customary in the semiconductor business, it
will in the future seek to convert its fabrication process technology to
larger wafer sizes, to smaller device geometries or to new or additional
suppliers in order to maintain or enhance its competitive position. Such
conversions entail inherent technological risks that could adversely affect
yields and delivery times and could have a material adverse impact on the
Company's operating results. To a considerable extent, the Company's ability
to execute its strategies will depend upon its ability to maintain and
enhance its advanced process technologies. As the Company does not presently
operate its own wafer fabrication or process development facility, the
Company depends upon silicon wafer manufacturers to provide the facilities
and support for its process development. In light of this dependency and the
intensely competitive nature of the semiconductor industry, there is no
assurance that either process technology development or timely product
introduction can be sustained in the future.
In addition, other unanticipated changes in or disruptions of the Company's
wafer supply arrangements could reduce product availability, increase cost or
impair product quality and reliability. Many of the factors that could
result in such changes are beyond the Company's control. For example, a
disruption of operations at Seiko
13
Epson's or UMC's manufacturing facilities as a result of a work stoppage,
fire, earthquake or other natural disaster, would cause delays in shipments
of the Company's products and would have a material adverse effect on the
Company's operating results.
The Company's finished silicon wafers are assembled and packaged by
independent subcontractors located in the Philippines, South Korea and
Malaysia, Hong Kong and the United States. Although the Company has not yet
experienced significant problems or interruptions in supply from its assembly
contractors, any prolonged work stoppages or other failure of these
contractors to supply finished products could have a material adverse effect
on the Company's operating results.
Because of the rapid rate of technological change in the semiconductor
industry, the Company's success will ultimately depend in large part on its
ability to introduce new products on a timely basis that meet a market need
at a competitive price and with acceptable margins as well as enhancing the
performance of its existing products. The success of new products, including
the Company's high-density product families, depends on a variety of factors,
including product selection, timely and efficient completion of product
design, timely and efficient implementation of manufacturing and assembly
processes, product performance, quality and reliability in the field and
effective sales and marketing. Because new product development commitments
must be made well in advance of sales, new product decisions must anticipate
both future demand and the technology that will be available to supply that
demand. New and enhanced products are continually being introduced into the
Company's markets by others, and these products can be expected to affect the
competitive environment in the markets in which they are introduced. There
is no assurance that the Company will be successful in enhancing its existing
products or in selecting, developing, manufacturing, marketing and selling
new products.
Future revenue growth will be largely dependent on market acceptance of the
Company's new and proprietary products, including its high-density product
families, and market acceptance of the Company's proprietary software
development tools. There can be no assurance that the Company's product and
process development efforts will be successful or that new products,
including the Company's high-density products, will continue to achieve
market acceptance. If the Company were unable to successfully define, develop
and introduce competitive new products in a timely manner, its future
operating results would be adversely affected.
The semiconductor industry is intensely competitive and is characterized by
rapid technological change, sudden price fluctuations, general price erosion,
rapid rates of product obsolescence, periodic shortages of materials and
manufacturing capacity and variations in manufacturing costs and yields. The
Company's competitive position is affected by all of these factors and by
industry competition for effective sales and distribution channels. The
Company's existing and potential competitors range from established major
domestic and international semiconductor companies to emerging companies.
Many of the Company's competitors have substantially greater financial,
technological, manufacturing, marketing and sales resources than the Company.
The Company faces direct competition from companies that have developed or
licensed similar technology and from licensees of the Company's products and
technology. The Company also faces indirect competition from a wide variety
of semiconductor companies offering products and solutions based on
alternative technologies. Although to date the Company has not experienced
significant competition from companies located outside the United States,
such companies may become a more significant competitive factor in the
future. As the Company and its current competitors seek to expand their
markets, competition may increase, which could have an adverse effect on the
Company's operating results. Competitors' development of new technologies
that have price/performance
14
characteristics superior to the Company's technologies could adversely affect
the Company's results of operations. There can be no assurance that the
Company will be able to develop and market new products successfully or that
the products introduced by others will not render the Company's products or
technologies non-competitive or obsolete. The Company expects that its
markets will become more competitive in the future.
In an effort to secure additional wafer supply, the Company may from time to
time consider various arrangements, including joint ventures with, minority
investments in, advanced purchase payments to, loans to or similar
arrangements with independent wafer manufacturers in exchange for committed
production capacity. Such arrangements are becoming common within the
industry as independent wafer manufacturers increasingly seek to require
their customers to share a portion of the cost of capital intensive wafer
fabrication facilities. In 1994, the Company entered into an advanced
production payment agreement with Seiko Epson pursuant to which it advanced a
total of $42 million to Seiko Epson. In September 1995, the Company entered
into an agreement with UMC under which it will invest a total of
approximately $53 million for a 10% equity interest in a separate Taiwanese
company (UICC) providing for the formation of a joint venture with UMC and
several other companies for the purpose of building and operating an advanced
semiconductor manufacturing facility. In March 1997, the Company entered
into a second advanced production payment agreement with Seiko Epson pursuant
to which it plans to advance up to $150 million to Seiko Epson. To the
extent the Company pursues any other such transactions with Seiko Epson, UMC
or any other wafer manufacturers, such transactions could entail even greater
levels of investment requiring the Company to seek additional equity or debt
financing to fund such activities. There can be no assurance that any such
additional funding could be obtained when needed or, if available, on terms
acceptable to the Company.
The Company's success depends in part on its proprietary technology. While
the Company attempts to protect its proprietary technology through patents,
copyrights and trade secrets, it believes that its success will depend more
upon technological expertise, continued development of new products, and
successful market penetration of its silicon and software products. There
can be no assurance that the Company will be able to protect its technology
or that competitors will not be able to develop similar technology
independently. The Company currently has a number of United States and
foreign patents and patent applications. There can be no assurance that the
claims allowed on any patents held by the Company will be sufficiently broad
to protect the Company's technology, or that any patents will issue from any
application pending or filed by the Company. In addition, there can be no
assurance that any patents issued to the Company will not be challenged,
invalidated or circumvented or that the rights granted thereunder will
provide competitive advantages to the Company.
The semiconductor industry is generally characterized by vigorous protection
and pursuit of intellectual property rights and positions, which have on
occasion resulted in protracted litigation that utilizes cash and management
resources, which can have a significant adverse effect on operating results.
The Company has received a letter from a semiconductor manufacturer stating
that it believes a number of its patents related to product packaging cover
certain products sold by the Company. While the manufacturer has offered to
license certain of such patents to the Company, there can be no assurance, on
this or any other claim which may be made against the Company, that the
Company could obtain a license on terms or under conditions that would be
favorable to the Company. In addition, there can be no assurance that other
intellectual property claims will not be made against the Company in the
future or that the Company will not be prohibited from using the technologies
subject to such claims or be required to obtain licenses and make
corresponding royalty payments for past or future use.
15
International revenues accounted for 47%, 48% and 49% of the Company's
revenues for fiscal 1995, 1996 and 1997, respectively. The Company believes
that international revenues will continue to represent a significant
percentage of revenues. International revenues and operations may be
adversely affected by the imposition of governmental controls, export license
requirements, restrictions on the export of technology, political
instability, trade restrictions, changes in tariffs and difficulties in
staffing and managing international operations.
The future success of the Company is dependent, in part, on its ability to
attract and retain highly qualified technical and management personnel,
particularly highly skilled engineers involved in new product, both silicon
and software, and process technology development. Competition for such
personnel is intense. There can be no assurance that the Company will be
able to retain its existing key technical and management personnel or attract
additional qualified employees in the future. The loss of key technical or
management personnel could delay product development cycles or otherwise have
a material adverse effect on the Company's business.
The Company currently depends on foreign manufacturers -- Seiko Epson, a
Japanese company, and UMC, a Taiwanese company -- for the manufacture of all
of its finished silicon wafers, and anticipates depending on UICC, a
Taiwanese company, for the manufacture of a portion of its finished silicon
wafers. In addition, after wafer manufacturing is completed and each wafer
is tested, products are assembled by subcontractors in South Korea, the
Philippines, Hong Kong, and Malaysia. Although the Company has not
experienced any interruption in supply from its subcontractors, the social
and political situations in these countries can be volatile, and any
prolonged work stoppages or other disruptions in the Company's ability to
manufacture and assemble its products would have a material adverse effect on
the Company's results of operations. Furthermore, economic risks, such as
changes in currency exchange rates, tax laws, tariffs, or freight rates, or
interruptions in air transportation, could have a material adverse effect on
the Company's results of operations.
EMPLOYEES
As of March 29, 1997, the Company had 531 full-time employees. The Company
believes that its future success will depend, in part, on its ability to
continue to attract and retain highly skilled technical, marketing and
management personnel.
None of the Company's employees is subject to a collective bargaining
agreement. The Company has never experienced a work stoppage and considers
its employee relations good.
ITEM 2. PROPERTIES
The Company's corporate offices, testing and principal research and design
facilities are located in two adjacent buildings owned by the Company in
Hillsboro, Oregon comprising a total of 90,000 square feet. The Company's
executive, administrative, marketing and production activities are also
located at these facilities. The Company leases a 41,000 square foot research
and design facility in Milpitas, California under a five-year term which
expires in August 1998.
The Company leases space in various locations in the United States for its
domestic sales offices, and also leases space in Hong Kong, London, Munich,
Paris, Seoul, Stockholm, Taipei and Tokyo for its international sales
offices. The Company owns a 13,000 square foot research and development
facility and approximately 6,000 square feet of dormitory facilities in
Shanghai.
16
ITEM 3. LEGAL PROCEEDINGS.
There are no material pending legal proceedings to which the Company is a
party or to which any of its property is subject.
ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS.
Not applicable.
17
ITEM 4(a). EXECUTIVE OFFICERS OF THE REGISTRANT.
As of June 12, 1997, the executive officers of the Company are as set forth
below.
Name Age Position
- - - ---------------------- --- ------------------------------------------
Cyrus Y. Tsui 51 President, Chief Executive Officer and
Chairman of the Board
Steven A. Laub 38 Senior Vice President and Chief Operating Officer
Stephen A. Skaggs 34 Senior Vice President, Chief Financial Officer and
Secretary
Jonathan K. Yu 56 Corporate Vice President, Business Development
Martin R. Baker 41 Vice President and General Counsel
Randy D. Baker 38 Vice President, Manufacturing
Albert L. Chan 47 Vice President, California Product Development
Stephen M. Donovan 46 Vice President, International Sales
Paul T. Kollar 51 Vice President, Sales
Rodney F. Sloss 53 Vice President, Finance
Kenneth K. Yu 49 Vice President and Managing Director,
Lattice Asia
Executive officers of the Company are appointed by the Board of Directors to
serve at the discretion of the Board and hold office until the officers'
successors are appointed.
Cyrus Y. Tsui joined the Company in September 1988 as President, Chief
Executive Officer and Director, and in March 1991 was named Chairman of the
Board. From 1987 until he joined the Company, Mr. Tsui was Corporate Vice
President and General Manager of the Programmable Logic Division of AMD. He
was Vice President and General Manager of the Commercial Products Division of
Monolithic Memories Incorporated from 1983 until the merger with AMD in 1987.
Mr. Tsui has held technical and managerial positions in the semiconductor
industry for over 25 years. He has worked in the programmable logic industry
since its inception.
Steven A. Laub joined the Company in June 1990 as Vice President and General
Manager. He was elected Senior Vice President and Chief Operating Officer in
August 1996.
18
Stephen A. Skaggs joined the Company in December 1992 as Director, Corporate
Development. He was elected Senior Vice President, Chief Financial Officer
and Secretary in August 1996. From 1984 until he joined the Company, Mr.
Skaggs was with Bain & Company, Inc., an international management consulting
firm.
Jonathan K. Yu joined the Company in February 1992 as Vice President,
Operations. He was elected Corporate Vice President, Business Development in
August 1996. Mr. Yu has held technical and managerial positions in the
semiconductor industry for over 30 years.
Martin R. Baker joined the Company in January 1997 as Vice President and
General Counsel. From 1991 until he joined the Company, Mr. Baker held legal
positions with Altera Corporation.
Randy D. Baker joined the Company in April 1985 as Manager, Manufacturing and
was promoted in 1988 to Director, Manufacturing. He was elected Vice
President, Manufacturing in August 1996. Mr. Baker has worked in the
semiconductor industry for over 15 years.
Albert L. Chan joined the Company in May 1989 as California Design Center
Manager and was promoted in 1991 to Director, California Product Development
Center. He was elected Vice President, California Product Development in
August 1993. Mr. Chan has worked in the programmable logic industry since
1983.
Stephen M. Donovan joined the Company in October 1989 and has served as
Director of Marketing and Director of International Sales. He was elected
Vice President, International Sales in August 1993. Mr. Donovan has worked
in the programmable logic industry since 1982.
Paul T. Kollar joined the Company in November 1985 and since that time has
served as Vice President, Sales and Vice President, Sales and Marketing. Mr.
Kollar has worked in the semiconductor industry for over 25 years.
Rodney F. Sloss joined the Company in May 1994 as Vice President, Finance.
From 1992 to 1994, Mr. Sloss served as Chief Financial Officer of The
Alexander Haagen Company, a real estate developer.
Kenneth K. Yu joined the Company in January 1991 as Director of Process
Technology. He has served as Managing Director, Lattice Asia since November
1992 and was elected Vice President, Lattice Asia in August 1993. Mr. Yu has
held technical and managerial positions in the semicondutor industry for over
20 years.
19
PART II
ITEM 5. MARKET FOR THE REGISTRANT'S COMMON STOCK AND
RELATED STOCKHOLDER MATTERS.
The Company's common stock is traded on the over-the-counter market and
prices are quoted on the Nasdaq National Market under the symbol "LSCC". The
following table sets forth the high and low sale prices for the common stock
for the last two fiscal years and for the period since March 29, 1997. On
June 12, 1997, the last reported sale price of the common stock was $55 3/8.
All share prices have been adjusted for the three-for-two stock split
effected in the form of a stock dividend which was paid on July 6, 1993. As
of June 12, 1997, the Company had approximately 290 beneficial owners of its
common stock.
High Low
------- -------
Fiscal 1996:
First Quarter ................................. $37 1/8 $23
Second Quarter ................................ 43 28 7/8
Third Quarter ................................. 42 1/8 27 5/8
Fourth Quarter ................................ 37 3/8 26 3/8
Fiscal 1997:
First Quarter ................................. $36 1/4 $21 5/8
Second Quarter ................................ 31 1/2 19 3/4
Third Quarter ................................. 47 27 1/2
Fourth Quarter ................................ 54 7/8 39 3/4
Fiscal 1998:
First Quarter (through June 12, 1997) ......... $62 5/8 $43 1/4
The payment of dividends on the common stock is within the discretion of the
Company's Board of Directors. The Company intends to retain earnings to
finance the growth of its business. The Company has not paid cash dividends
on its common stock and the Board of Directors does not expect to declare
cash dividends on the common stock in the near future.
ITEM 6. SELECTED FINANCIAL DATA.
The information required by this Item is set forth in the Company's 1997
Annual Report to Stockholders at page 17 under the caption "Selected
Financial Data", which information is incorporated herein by reference.
20
ITEM 7. MANAGEMENT'S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND
RESULTS OF OPERATIONS.
The information required by this Item is set forth in the Company's 1997
Annual Report to Stockholders at pages 14 through 16 under the caption
"Management's Discussion and Analysis of Financial Condition and Results of
Operations", which information is incorporated herein by reference.
ITEM 8. FINANCIAL STATEMENTS AND SUPPLEMENTARY DATA.
FINANCIAL STATEMENTS
The information required by this Item is set forth in the Company's 1997
Annual Report to Stockholders, at pages 18 through 28, which information is
incorporated herein by reference.
PAGE
----
FINANCIAL STATEMENT SCHEDULES
Report of Independent Accountants on Financial
Statement Schedule ......................................... S-1
Schedule VIII - Valuation and qualifying accounts ............ S-2
No other schedules are included because the required information is
inapplicable, not required or is presented in the financial statements or
related notes thereto.
ITEM 9. CHANGES IN AND DISAGREEMENTS WITH ACCOUNTANTS
ON ACCOUNTING AND FINANCIAL DISCLOSURE.
Not applicable.
With the exception of the information expressly incorporated by reference
from the Annual Report to Stockholders into Parts II and IV of this Form
10-K, the Company's Annual Report to Stockholders is not to be deemed filed
as part of this Report.
21
PART III
Certain information required by Part III is omitted from this Report in that
the Company will file its definitive proxy statement for the Annual Meeting
of Stockholders to be held on August 11, 1997, pursuant to Regulation 14A of
the Securities Exchange Act of 1934 (the "Proxy Statement"), not later than
120 days after the end of the fiscal year covered by this Report, and certain
information included in the Proxy Statement is incorporated herein by
reference.
ITEM 10. DIRECTORS AND EXECUTIVE OFFICERS OF THE REGISTRANT.
The information required by this item with respect to directors of the
Company is included under "Proposal 1: Election of Directors" in the
Company's Proxy Statement and is incorporated herein by reference.
Information with respect to executive officers of the Company is included
under Item 4(a) of Part I of this Report and is incorporated herein by
reference.
ITEM 11. EXECUTIVE COMPENSATION.
The information required by this item with respect to executive compensation
is included under "Proposal 1: Election of Directors," "Executive
Compensation" and "Comparison of Total Cumulative Stockholder Return" in the
Company's Proxy Statement and is incorporated herein by reference.
ITEM 12. SECURITY OWNERSHIP OF CERTAIN BENEFICIAL OWNERS AND MANAGEMENT.
The information required by this Item is included in the Company's Proxy
Statement under the caption "Security Ownership of Certain Beneficial Owners
and Management" and is incorporated herein by reference.
ITEM 13. CERTAIN RELATIONSHIPS AND RELATED TRANSACTIONS.
The information required by this Item is included under "Proposal 1: Election
of Directors - Transactions with Management" in the Company's Proxy Statement
and is incorporated herein by reference.
22
PART IV
ITEM 14. EXHIBITS, FINANCIAL STATEMENT SCHEDULES AND
REPORTS ON FORM 8-K.
(a)(1) and (2) FINANCIAL STATEMENTS AND FINANCIAL STATEMENT SCHEDULES.
The information required by this item is included under
Item 8 of this Report.
(a)(3) EXHIBITS.
3.1 Certificate of Incorporation, as amended (Incorporated
by reference to Exhibit 3.1 filed with the Company's
Annual Report on Form 10-K for the fiscal year ended
March 31, 1990).
3.2 Bylaws, as amended (Incorporated by reference to
Exhibit 3.2 filed with the Company's Annual Report
on Form 10-K for the fiscal year ended March 30,
1991).
4.1 Preferred Shares Rights Agreement dated as of
September 11, 1991 between Lattice Semiconductor
Corporation and First Interstate Bank of Oregon,
N.A., as Rights Agent (Incorporated by reference to
Exhibit 1 filed with the Company's Registration
Statement on Form 8-A on September 13, 1991).
10.3 Patent License Agreement dated November 10, 1989
between Monolithic Memories, Inc. and Lattice
Semiconductor Corporation, as amended (Incorporated
by reference to Exhibit 10.3, File No. 33-31231).(1)
10.4 Production and Non-exclusive License Agreement dated
January 19, 1987 between Lattice Semiconductor
Corporation and SGS Semiconductor Corporation
(Incorporated by reference to Exhibit 10.4, File No.
33-31231).(1)
10.5 Manufacturing Agreement dated February 18, 1988
between Lattice Semiconductor Corporation and S MOS
Systems, Inc. (Incorporated by reference to Exhibit
10.5, File No. 33-35427).(1)
10.6 Extension effective December 31, 1990 to Manufacturing
Agreement dated February 18, 1988 between Lattice
Semiconductor Corporation and S MOS Systems, Inc.
(Incorporated by reference to Exhibit 10.6 filed
with the Company's Annual Report on Form 10-K for
the fiscal year ended March 30, 1991).
10.7 Form of Distributor Agreement (Incorporated by
reference to Exhibit 10.6, File No. 33-31231).
23
10.8 Form of Representative Agreement (Incorporated by
reference to Exhibit 10.7, File No. 33-31231).
10.9 * Lattice Semiconductor Corporation 1988 Stock
Incentive Plan, as amended (Incorporated by
reference to Exhibit 10.9 filed with the Company's
Annual Report on Form 10-K for the fiscal year ended
March 28, 1992).
10.10 * Form of Stock Option Agreement (Incorporated by
reference to Exhibit 10.9, File No. 33-31231).
10.11 * Employment Letter dated September 2, 1988 from
Lattice Semiconductor Corporation to Cyrus Y. Tsui
(Incorporated by reference to Exhibit 10.10, File No.
33-31231).
10.12 Form of Proprietary Rights Agreement (Incorporated by
reference Exhibit 10.11, File No. 33-31231).
10.13 * Outside Directors Compensation Plan (Incorporated by
reference to Exhibit 10.12, File No. 33-31231).
10.14 * Amended Outside Directors Stock Option Plan
(Incorporated by reference to Exhibit 10.13, File No.
33-35427).
10.15 * 1993 Outside Directors Stock Option Plan
(Incorporated by reference to Exhibit 10.15 filed
with the Company's Annual Report on Form 10-K for the
fiscal year ended April 3, 1993).
10.16 * Employee Stock Purchase Plan, as amended
(Incorporated by reference to Exhibit 10.16 filed
with the Company's Annual Report on Form 10-K for
the fiscal year ended April 3, 1993).
10.17 Advance Production Payment Agreement dated July 5,
1994 among Lattice Semiconductor Corporation and
Seiko Epson Corporation and S-MOS Systems, Inc.
(Incorporated by reference to Exhibit 10.17 filed
with the Company's Annual Report on Form 10-K for
the fiscal year ended April 1, 1995). (1)
10.18 Engineering Payment Agreement dated July 5, 1994 among
Lattice Semiconductor Corporation and Seiko Epson
Corporation and S-MOS Systems, Inc. (Incorporated by
reference to Exhibit 10.18 filed with the Company's
Annual Report on Form 10-K for the fiscal year ended
April 1, 1995). (1)
24
10.19 Bridge Capacity Letter dated September 12, 1995
between Lattice Semiconductor Corporation and United
Microelectronics Corporation. (Incorporated by
reference to Exhibit 10.1 filed with the Company's
Current Report on Form 8-K dated September 28,
1995)(1).
10.20 Foundry Venture Side Letter dated September 13, 1995
among Lattice Semiconductor Corporation, United
Microelectronics Corporation and FabVen
(Incorporated by reference to Exhibit 10.2 filed
with the Company's Current Report on Form 8-K dated
September 28, 1995)(1).
10.21 FabVen Foundry Capacity Agreement dated as of August
___, 1995 among FabVen, United Microelectronics
Corporation and Lattice Semiconductor Corporation
(Incorporated by reference to Exhibit 10.3 filed
with the Company's Current Report on Form 8-K dated
September 28, 1995)(1).
10.22 Foundry Venture Agreement dated as of August ___, 1995,
between Lattice Semiconductor Corporation and United
Microelectronics Corporation (Incorporated by
reference to Exhibit 10.4 filed with the Company's
Current Report on Form 8-K dated September 28,
1995)(1).
10.23 Advance Production Payment Agreement dated March 17,
1997 among Lattice Semiconductor Corporation and
Seiko Epson Corporation and S MOS Systems, Inc. (2)
10.24 Lattice Semiconductor Corporation 1996 Stock Incentive
Plan (Incorporated by reference to Exhibit 4.1 filed
on Form S-8 dated November 7, 1996).
11.1 Computation of Net Income Per Share.
13.1 1997 Annual Report to Stockholders
21.1 Subsidiaries of the Registrant.
23.1 Consent of Independent Accountants.
24.1 Power of Attorney (see pages 27-28).
27 Financial Data Schedule for Twelve Months Ended March
29, 1997.
______________
(1) Pursuant to Rule 24b-2 under the Securities Exchange Act of 1934,
confidential treatment has been granted to portions of this
exhibit, which portions have been deleted and filed separately
with the Securities and Exchange Commission.
(2) Pursuant to Rule 24b-2 under the Securities Exchange Act of 1934,
confidential treatment has been requested for portions of this
exhibit, which portions have been deleted and filed separately with
the Securities and Exchange Commission.
25
* Management contract or compensatory plan or arrangement required to be
filed as an Exhibit to this Annual Report on Form 10-K pursuant
to Item 14(c) thereof.
(b) No reports on Form 8-K were filed during the last quarter of fiscal 1997.
(c) See (a)(3) above.
(d) See (a)(1) and (2) above.
26
SIGNATURES
Pursuant to the requirements of Section 13 or 15(d) of the Securities
Exchange Act of 1934, the Registrant has duly caused this Report to be signed
on its behalf by the undersigned, thereunto duly authorized, in the City of
Hillsboro, State of Oregon, on the 26th of June, 1997.
LATTICE SEMICONDUCTOR CORPORATION
By: /s/Stephen A. Skaggs
-----------------------------
Stephen A. Skaggs, Senior Vice
President, Chief Financial Officer
and Secretary
POWER OF ATTORNEY
KNOW ALL PERSONS BY THESE PRESENTS, that each person whose signature appears
below constitutes and appoints Cyrus Y. Tsui and Stephen A. Skaggs, jointly
and severally, his attorneys-in-fact, each with the power of substitution,
for him in any and all capacities, to sign any amendments to this Report on
Form 10-K, and to file the same, with exhibits thereto and other documents in
connection therewith, with the Securities and Exchange Commission, hereby
ratifying and confirming all that each of said attorneys-in-fact, or his
substitute or substitutes, may do or cause to be done by virtue hereof.
Pursuant to the requirements of the Securities Exchange Act of 1934, this
Report has been signed below by the following persons on the 26th day of
June, 1997 on behalf of the Registrant and in the capacities indicated:
Signature Title
- - - ----------------------------- ---------------------------------------
/s/Cyrus Y. Tsui President, Chief Executive Officer
- - - --------------------------- and Chairman of the Board (Principal
Cyrus Y. Tsui Executive Officer)
/s/Stephen A. Skaggs Senior Vice President, Chief Financial
- - - --------------------------- Officer and Secretary (Principal
Stephen A. Skaggs Financial Officer)
/s/Mark O. Hatfield Director
- - - ---------------------------
Mark O. Hatfield
/s/Daniel S. Hauer Director
- - - ---------------------------
Daniel S. Hauer
27
Signature Title
- - - ----------------------------- ---------------------------------------
/s/Harry A. Merlo Director
- - - ---------------------------
Harry A. Merlo
/s/Larry W. Sonsini Director
- - - ---------------------------
Larry W. Sonsini
/s/Douglas C. Strain Director
- - - ---------------------------
Douglas C. Strain
28
REPORT OF INDEPENDENT ACCOUNTANTS
ON FINANCIAL STATEMENT SCHEDULE
To the Board of Directors
of Lattice Semiconductor Corporation
Our audits of the consolidated financial statements referred to in our report
dated April 16, 1997 appearing in the 1997 Annual Report to Stockholders of
Lattice Semiconductor Corporation (which report and consolidated financial
statements are incorporated by reference in this Annual Report on Form 10-K)
also included an audit of the Financial Statement Schedule listed in Item
14(a)(2) of this Form 10-K. In our opinion, this Financial Statement Schedule
presents fairly, in all material respects, the information set forth therein
when read in conjunction with the related consolidated financial statements.
/s/ Price Waterhouse LLP
PRICE WATERHOUSE LLP
Portland, Oregon
April 16, 1997
S-1
SCHEDULE VIII
LATTICE SEMICONDUCTOR CORPORATION
VALUATION AND QUALIFYING ACCOUNTS
(IN THOUSANDS)
COLUMN A COLUMN B COLUMN C COLUMN D COLUMN E COLUMN F
CHARGED TO
BALANCE AT CHARGED TO OTHER WRITE-OFFS BALANCE
BEGINNING OF COSTS AND ACCOUNTS NET OF AT END OF
CLASSIFICATION PERIOD EXPENSES (DESCRIBE) RECOVERIES PERIOD
-------------- ------------ ---------- ---------- ---------- ---------
Year ended April 1, 1995:
Allowance for deferred tax asset .......... $2,420 $ 399 -- -- $2,819
Allowance for doubtful accounts ........... 697 75 -- (29) 743
------ ------ ---- ----- ------
$3,117 $ 474 $ -- $ (29) $3,562
------ ------ ---- ----- ------
------ ------ ---- ----- ------
Year ended March 30, 1996:
Allowance for deferred tax asset .......... $2,819 $(483) -- -- $2,336
Allowance for doubtful accounts ........... 743 70 -- (13) 800
------ ------ ---- ----- ------
$3,562 $ (413) $ -- $ (13) $3,136
------ ------ ---- ----- ------
------ ------ ---- ----- ------
Year ended March 29, 1997:
Allowance for deferred tax asset .......... $2,336 $(340) -- -- $1,996
Allowance for doubtful accounts ........... 800 70 -- 4 874
------ ------ ---- ----- ------
$3,136 $ (270) $ -- $ 4 $2,870
------ ------ ---- ----- ------
------ ------ ---- ----- ------
S-2