EXHIBIT 10.14
INTEL CONFIDENTIAL
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INTEL/CHIPPAC LIMITED
ASSEMBLY SERVICES AGREEMENT
(Replacement Agreement for Intel Agreement No. 0995ELR001)
This Agreement ("Agreement") is entered into this 5th day of August, 1999 and
shall become effective upon the Effective Date, by and between Intel Corporation
("Intel"), a Delaware corporation with its principal offices located at 2200
Mission College Boulevard, Santa Clara, California 95052, and ChipPAC Limited, a
British Virgin Islands corporation with principal offices located at Craigmuir
Chambers, Road Town, Tortola, British Virgin Islands ("ChipPAC"). Intel and
ChipPAC are sometimes collectively referred to as the "Parties" or singularly as
a "Party". "Effective Date" means the date of consummation of the transactions
contemplated by that certain Agreement and Plan of Recapitalization and Merger
dated as of March 13, 1999, as amended, by and among Hyundai Electronics
Industries Company, Ltd., Hyundai Electronics America, ChipPAC, Inc. and ChipPAC
Merger Corp.
RECITALS:
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WHEREAS, Intel desires to enter into a contract assembly and test arrangement
with ChipPAC as more specifically described herein.
WHEREAS, ChipPAC is in the business of doing contract assembly and test work for
integrated circuit manufacturers and desires to perform such services for Intel.
WHEREAS, the Parties desire to set forth below the conditions and covenants
under which such work shall be performed.
NOW THEREFORE, in consideration of the mutual covenants herein contained, the
Parties agree as follows:
1. DEFINITIONS
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1.1 "[redacted*]" shall mean Intel's chipset products utilizing the
[redacted*] packaging process.
1.2 "[redacted*]" shall mean Intel's chipset products utilizing the
[redacted*] packaging process.
1.3 "[redacted*]" shall mean the chipset products utilizing the
[redacted] packaging process.
*Confidential treatment requested.
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1.4 "Die Product" shall mean an Intel Product in an unassembled form,
without packaging, specified in Exhibit D, and provided by Intel to
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ChipPAC under this Agreement in order for ChipPAC to perform the
Services.
1.5 "Die Product Specification" shall mean the technical information for
each Intel Product which ChipPAC is authorized to handle under this
Agreement.
1.6 "Facility" shall mean the Intel work area in the factory provided by
ChipPAC to perform the Services as defined below.
1.7 "Intel Product" shall mean the finished product which is sold by Intel
in a packaged form and which contains the die of the related Die
Product, and which ChipPAC processes or manufactures on behalf of
Intel which complies with the Specifications/ Performance Standards
specified in Exhibit B.
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1.8 "Intel Product Data Sheet" shall mean the technical information for
each Intel Product supplied by Intel to purchasers of Intel Products.
1.9 "Leadframes" shall mean the leadframes that ChipPAC shall order as
Piece Parts in anticipation of fulfilling Intel's orders for
[redacted*] and [redacted*].
1.10 "Leadtime" shall mean TPT plus transit time to Intel.
1.11 "Leadtime Procurement Period" shall mean the procurement of Piece
Parts during the Leadtime period.
1.12 "LIPAS" (Line Item Performance Against Schedule) shall mean the number
of Line Items that shipped in a given week divided by the number of
Line Items scheduled by ChipPAC to be shipped during the same week per
Intel's forecast.
1.13 "Non Data Sheet Functionality" shall mean (a) features, instructions,
operating modes, and other functions which may be contained in the
Intel Product and the Die Product but which Intel does not document
and which are not required for the Intel Product and the Die Product
to comply with the related Intel Product Data Sheet, and (b) internal
nodes and signals which are not accessible at the bond pads of the Die
Product.
1.14 "Piece Parts" shall mean all materials procured and furnished by
ChipPAC in order to perform the Services under this Agreement.
*Confidential treatment requested.
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1.15 "Rejects" shall mean the product produced by ChipPAC which do not
comply with the Specifications and Performance Standards specified in
Exhibit B, are damaged or are otherwise returned to ChipPAC or
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rejected by Intel.
1.16 "Release" shall mean Intel's purchase order or change order accepting
ChipPAC's offer to ship a definite quantity of Intel Products or to
provide Services to a specified schedule and pricing.
1.17 "Service(s)" shall mean the work to be performed as specified in
Exhibit A in compliance with the Specifications/Performance Standards
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specified in Exhibit B.
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1.18 "Substrates" shall mean the substrate materials that ChipPAC shall
order as Piece Parts in anticipation of fulfilling Intel's orders for
[redacted*] Products.
1.19 "Through Put Time" (TPT) shall mean the number of calendar days
required to manufacture the Intel Product, starting when the Wafers or
Die Product are released from inventory at ChipPAC and ending when the
Intel Products are shipped out of ChipPAC.
1.20 "Wafer" shall mean Intel's substrate material that contains unscribed
Die Product that have been sorted by Intel as Die Product which has
passed the sort criteria for the Intel Product ("non-inked") and Die
Product which has failed the sort criteria for the Intel Product
("inked").
1.21 "Work in Process" referred to hereinafter as "WIP".
2. STATEMENT OF WORK
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2.1 ChipPAC will provide all facilities, equipment, material, manpower and
expertise necessary to perform the Services according to Intel
requirements and specifications as referenced in Exhibits A and B.
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2.2 Intel shall supply ChipPAC with all Wafers and Die Product.
2.3 ChipPAC shall provide at ChipPAC's expense all Piece Parts, supplies
and peripheral products, including leadframes, required for ChipPAC to
perform the Services.
2.4 ChipPAC shall perform the Services in accordance with Intel's
requirements and specifications as specified in Exhibits A and B.
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2.5 ChipPAC shall at least meet the minimum yields and maximum TPT
specified in Exhibit C, with a goal of continually improving both
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yield and TPT.
*Confidential treatment requested.
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2.6 ChipPAC shall adhere to Intel's procedures with respect to security,
traceability and accountability as specified herein.
3. PRE-PRODUCTION
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3.1 In the event that Intel determines a need to have certain Intel
Products produced by ChipPAC on a limited scale or as prototypes in
order to qualify those Intel Products or the process involved or to
produce samples of the Intel Products ("Pre-Production Parts"), prior
to beginning full production, Intel and ChipPAC shall agree on the
quantity, specifications, pricing, Leadtime and other requirements for
each such Pre-Production Part. All orders for Pre-Production Parts
must first be authorized in writing by Intel. Once Intel has
qualified and accepted the Pre-Production Parts, these may be ordered
as Intel Products under the Agreement.
3.2 If Intel cancels all or part of any order for Pre-Production Parts,
Intel shall pay for the related WIP for the canceled order, as
outlined in Exhibit E, Cancellation Liability.
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3.3 Intel recognizes that yields for Pre-Production Parts may be difficult
to control. If ChipPAC's build amount does not provide sufficient
quantities to provide the quantity ordered by Intel, and the
outstanding amount is less than [redacted*] of the ordered quantity,
Intel may either cancel the balance of the order without penalty, or
allow ChipPAC to provide the balance of the order at a later date, not
to exceed fourteen (14) days from the date Intel provides replacement
Die Product.
3.4 ChipPAC warrants that Pre-Production Parts shall meet design test
vectors and be free of manufacturing defects, but otherwise are
provided "AS IS".
4. OWNERSHIP
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4.1 All Wafers and Die Product shall be held by ChipPAC for the sole
benefit of Intel. Ownership of Wafers and Die Product shall remain
with Intel. ChipPAC acknowledges that Intel retains an ownership
interest in the Wafers and Die Product and agrees to assist Intel in
perfecting said security interest under the Uniform Commercial Code
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and other relevant laws, at Intel's request. Ownership of all Rejects
shall remain with Intel.
5. CONFIDENTIALITY AND PUBLICITY
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5.1 Any confidential information to be exchanged between the Parties shall
be governed by the terms of the Corporate Non-Disclosure Agreement
(CNDA) number 0875665, which ChipPAC agrees to be bound by. At a
minimum, ChipPAC agrees to maintain such information in confidence,
pursuant to the terms of the above-referenced CNDA,
*Confidential Treatment requested.
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to take all reasonable precautions to prevent unauthorized disclosure
and to use such information only within the scope of this Agreement
until the information becomes publicly available through no fault of
ChipPAC. Examples of confidential information include, but are not
limited to, Wafers, Die Product, Die Product Specifications, yield,
probe characteristics, number of Wafers, and number of Die Product.
5.2 ChipPAC is responsible for (i) secure storage in a segregated
Facility, handling, processing and return of Intel Product
incorporating Die Product, and (ii) the return (or certified
destruction) of all scrap/Rejects to Intel. ChipPAC will be liable
for any loss, including, but not limited to, theft, destruction, and
deterioration.
5.3 ChipPAC's Facility, manufacturing and wafer processing areas must be
secure and accessed only by ChipPAC's employees or contractors on a
need-to-know basis. Any third party, including contract employees,
involved in any aspect of Wafer or Die Product shipping, storage,
security, processing, assembly, or handling must sign a Non-Disclosure
Agreement with Intel.
5.4 ChipPAC's employees who access Intel's premises may be required to
sign a separate non-disclosure agreement prior to admittance to
Intel's premises.
5.5 ChipPAC warrants that no information disclosed by ChipPAC to Intel, in
any form whatsoever, is the confidential information of any other
party without written authorization from that Party.
5.6 Neither Party may use the other Party's name in advertisements, news
releases, publicity statements, on the internet, or otherwise disclose
the existence or content of this Agreement, without the other's prior
written consent.
6. DELIVERY, RELEASES AND SCHEDULING
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6.1 Intel shall provide ChipPAC with a rolling [redacted*] operating
forecast of its requirements every week. An Intel Work Week Calendar
sample is attached as Exhibit G.
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6.2 Response: ChipPAC shall provide a written response to Intel's
[redacted*] requirements forecast letter within seven (7) working
days after receipt. If no response is received by Intel in this time
period, then the forecast is deemed to be approved by ChipPAC.
6.3 ChipPAC shall use the forecast only as a guide to adequately prepare
for Intel's anticipated requirements. Intel is not obligated to
purchase any specific business under this Agreement. Intel's
forecasts are subject to change and are not commitments. ChipPAC
understands that Intel's demand is dependent on market and
*Confidential treatment requested.
-5-
other factors beyond Intel's control and this may result in demand
being reduced, increased or eliminated.
6.4 ChipPAC shall meet the Intel unit requirements as set forth in the
shipping Release for the applicable purchase order as acknowledged by
ChipPAC as specified in paragraph 6.2 above.
6.5 Intel shall place with ChipPAC a Release for each Intel Product by the
minimum Leadtime required, specifying quantity, delivery date and
delivery place. ChipPAC agrees to acknowledge in writing each Release
within five (5) working days. ChipPac shall make weekly delivery
commitments by Line Item for the weekly Intel requests and monthly
delivery commitments by Line Item for the remaining months of the
forecast period. ChipPAC's delivery commitment shall be firm for the
Leadtime Procurement Period. Intel may make changes to its Releases at
any time in the form of "Demand Exceptions". Such Demand Exception
changes shall be sent immediately to ChipPAC in writing by fax or
other electronic means. ChipPAC must provide to Intel a written
response to Intel's Demand Exceptions via fax or e-mail within twenty-
four (24) hours after receipt of the Demand Exception changes. At such
time as Intel receives ChipPAC's committed response to the Demand
Exceptions, Intel shall update the Release accordingly. Leadtime
Procurement Period for [redacted*] is [redacted*] weeks.
6.6 ChipPAC agrees that all orders for Intel Products will ship on the
exact date specified. In the event that an order shipment is going to
be late, Intel must be notified as soon as ChipPAC is aware that the
Intel Product will not meet its committed ship date. Partial shipments
must be authorized by Intel and are counted as late shipments and will
only be considered complete when all Intel Products for that order
have been received. If shipments are late by more than seven (7) days,
at no fault of Intel, at Intel's option, Intel can cancel the order
with no charge. ChipPAC will be responsible for any costs incurred by
Intel in obtaining cover in the event of such order cancellation.
Intel shall have no obligation for orders shipped more than seven (7)
days late.
6.7 ChipPAC shall promptly notify Intel if ChipPAC is unable to perform
Services or deliver orders as scheduled and shall state the reasons
for such non-delivery or non performance. Such notification by
ChipPAC shall not affect Intel's termination rights.
6.8 Delivery Performance. ChipPAC's LIPAS performance shall be 100%. If
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ChipPAC's LIPAS performance falls below 100% for any reason, at no
fault of Intel, then ChipPAC shall promptly implement a corrective
action plan approved by Intel to bring LIPAS back into 100%
compliance. On-time deliveries for LIPAS performance measurement are
defined as ChipPAC shipping the Intel Product units that are due for
that week's delivery up to [redacted*] days early but [redacted*] days
late from the
*Confidential treatment requested.
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committed ship date specified on the purchase order. If ChipPAC's
delivery is [redacted*] or more days late, a [redacted*] discount
shall apply to the specific line items that are shipped late.
6.9 Intel may place any portion of a Release on hold by notice which shall
take effect immediately upon receipt. Releases placed on hold will be
rescheduled or canceled within a reasonable time (to be mutually
agreed upon by Intel and ChipPAC).
6.10 [redacted*] At a minimum, ChipPAC shall provide ship dates based on
TPT after receipt of a Release. For purposes of determining ship date
TPT, the date that a Release is sent (by fax, electronic means or
mail) will be the starting point for calculating the TPT.
6.11 Intel-requested or Intel-approved changes that result in ship date
changes will be reflected on a written change order to the Release
showing the revised ship and delivery dates.
6.12 ChipPAC shall maintain a safety stock of Piece Parts including
Leadframes and Substrates in sufficient quantity to maintain
production in accordance with the then-current Intel forecasts of four
(4) consecutive weeks for [redacted*] and [redacted*] packages and six
(6) consecutive weeks for new packages such as [redacted*] ("Safety
Stock Level"), in addition to the quantity specified on the then
current Release, unless otherwise requested by Intel in writing. Intel
shall be responsible for the cost of the Safety Stock Level for the
Leadframes and Substrates. All other Piece Part liability is covered
by paragraph 6.13 below.
6.13 Cancellation. If Intel cancels all or part of any order for Intel
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Products, Intel shall pay for the related WIP for the canceled order,
as outlined in Exhibit E, Cancellation Liability.
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6.14 Rescheduling. Intel may at any time, not later than seven (7) days.
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before the scheduled delivery date, reschedule any Release line item
from such scheduled delivery date to another date. Intel will be
liable only for the Piece Parts ordered relating to the specific
Release line item as outlined in Exhibit E, Cancellation Liability.
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Intel may also place all or any part of an order on hold, which shall
take place immediately upon receipt of notice by ChipPAC. Orders
placed on hold shall be canceled or rescheduled within a reasonable
time.
6.15 ChipPAC Notice. ChipPAC shall promptly notify Intel if ChipPAC is
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unable to make any scheduled delivery, and shall state the reasons.
*Confidential treatment requested.
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7. REPORTING
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7.1 ChipPAC shall provide Intel with a weekly report of all inventories
(including Die Product inventory), production schedule status, WIP
inventory, shipment, and any and all engineering and quality data
required for yield loss analysis to a designated Intel Representative
at Intel ISSL. This report must be in Intel's possession by 12:00
noon each Monday (Korean time) for the previous week. Intel may at
any time, upon one (1) business day's notice to ChipPAC, conduct a
physical inventory of all such Wafer, Die Product, Intel Products, WIP
and/or Rejects in the possession of ChipPAC.
7.2 At Intel's option, ChipPAC shall provide the Intel Program Manager,
with a soft copy or hard copy of monthly reports to a designated Intel
representative of all shipouts, ending-on-hand inventories (including
Wafer and Die Product inventory), Rejects, and units in-transit out of
production Facility to Intel. This report must be in Intel's
possession on the Intel month-end Friday by the end of the business
day (U.S. Pacific Time). Intel may at any time, upon one (1) business
day's notice to ChipPAC, cycle count and/or audit inventory all such
Wafers and Die Product, Intel Product and/or Rejects in the possession
of ChipPAC.
8. PRICE AND PAYMENT
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8.1 For the [redacted*] products there is no non-recurring engineering
("NRE") charges. For future products, the parties may negotiate NRE
charges to be paid by Intel.
8.2 Prices charged by Hyundai, ChipPAC's predecessor, for the Services
during the one-year period from September 16, 1996 are specified in
Exhibit E. The pricing schedule specified in Exhibit E shall remain
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firm or decline for the one-year period from September 16, 1996 unless
process changes are made by Intel, in which case a revised pricing
schedule shall be mutually agreed to by both Parties. Notwithstanding
the above, in extraordinary circumstances wherein Intel requests
changes to the Intel Product that substantially affect the price or if
market factors have changed which substantially affect the price, the
Parties will negotiate a revised pricing schedule which shall be
mutually agreed to by both Parties.
8.3 Hyundai, ChipPAC's predecessor, warranted that prices set forth in
Exhibit E reflect [redacted*] in consideration of the volume of Intel
Product purchases forcast by Intel. [redacted*] Intel and ChipPAC
agree to review the pricing under this Agreement not less than every
ninety (90) days [redacted*], and that ChipPAC is successful in
continually reducing the pricing provided to Intel.
*Confidential treatment requested.
-8-
8.4 Invoices shall include: purchase order number, description of and
dates of Services provided, prices and extended totals. Payment shall
not constitute acceptance of Intel Products. Applicable taxes and
other charges such as duties, customs, tariffs, imposts and government
imposed surcharges shall be stated separately on ChipPAC's invoice.
8.5 Additional costs, beyond those described on Exhibit E, shall not be
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reimbursed without Intel's prior written approval.
8.6 ChipPAC shall provide invoices with each shipment to Intel. All such
invoices shall be paid by Intel in U.S. dollars, net thirty (30) days
from the receipt of an acceptable invoice. The invoice amounts shall
be calculated based on the pricing set forth in Exhibit E or such
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other pricing mutually agreed upon by Intel and ChipPAC.
9. QUALITY AND RELIABILITY
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9.1 Qualification Requirements. ChipPAC is responsible for meeting and
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maintaining Intel's Quality and Reliability (Q&R) requirements as
listed in the Specifications referenced in Exhibit B.
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9.2 Qualification Stresses and Testing. ChipPAC is responsible for
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performing all qualification stresses and testing as per the
Specifications referenced in Exhibit B, except for those stresses and
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tests which Intel and ChipPAC mutually agree will be performed by
Intel. These exceptions will be documented on any new product and/or
package introduction by Intel to ChipPAC.
9.3 Traceability. ChipPAC shall demonstrate to Intel that ChipPAC's
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traceability system tracks each Intel Product box and unit to a
specific fab, assembly and test lot traveler, and is capable of
tracing to where each Intel Product lot was shipped and on which day.
Traceability records shall be maintained for five (5) years.
9.4 Manufacturing and Monitoring. ChipPAC shall properly manufacture,
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monitor, test, and inspect all Intel Product and Rejects resulting
from the performance of the Services in accordance with the
specifications in Exhibits A and B. ChipPAC shall manufacture Intel
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Product only at the Facilities qualified by Intel and documented in
the specifications referenced in Exhibits A and B. ChipPAC may not
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move any portion of the manufacturing process to any other facility
except with the prior written approval of Intel.
9.5 Change Control. Requirements and specifications listed in Exhibits A
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and B define the change control baseline. ChipPAC shall notify Intel
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of any proposed changes from the change control baseline at least
one hundred and twenty (120) days prior to the receipt of affected
Intel Product at Intel, per the requirements in Change Control
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Specifications listed in Exhibit B. ChipPAC shall provide Intel with
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Q&R data supporting the proposed change and Intel Product samples at
least one hundred (100) days prior to the proposed implementation date
of the change. ChipPAC shall not make the proposed change without
Intel's prior written approval. ChipPAC is responsible for ensuring
that the Leadtime of affected Intel Products to Intel is met. In the
event Intel's customers, or Intel, reasonably determine not to accept
the proposed changes, ChipPAC shall not make such change(s).
9.6 Failure Analysis Correlation Request. When potentially defective
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Intel Product is returned to ChipPAC by Intel or Intel's customers,
ChipPAC shall promptly perform correlation and failure analysis
against the specifications referenced in Exhibit B, stop processing
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questionable Intel Product and implement corrective action on the
Intel Product and WIP. ChipPAC commits to resolve issues in accordance
with the following timing following receipt of initial failure report:
(a) Initial Correlation: Go/No-Go electrical or mechanical tests
shall be performed within five (5) calendar days of receipt. A
telephone report to Intel will be the timing end point. ChipPAC
shall follow-up with a summary of the testing and results. In the
event of Intel customers' going "lines-down" or approaching a
near "lines down" situation, Intel shall request initial
correlation testing reports to be completed within twenty-four
(24) hours of ChipPAC's receipt.
(b) Unless otherwise requested, ChipPAC shall complete, implement and
document failure analysis and/or stop processing questionable
Intel Product within twenty-five (25) calendar days of receipt.
(c) Unless otherwise requested, ChipPAC shall implement a root cause
corrective action plan within fifty-five (55) calendar days of
receipt.
ChipPAC agrees to provide failure analysis correlation request support
for up to three (3) years after last delivery of an Intel Product to
Intel.
9.7 Continuous Improvement. During the production life of each Intel
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Product, ChipPAC shall seek to continuously improve performance in the
areas of Q&R pursuant to the requirements and specifications listed in
Exhibits A and B. Both Parties shall meet regularly to review
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progress and define improvement actions and objectives. The meeting
frequency shall be as agreed by the Parties. During the production
period, ChipPAC shall adequately staff to sustain and manage the Intel
program including supporting programs of continuous improvement.
9.8 Corrective Action.
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(a) Intel may periodically sample Intel Product and use the data
obtained to determine if the Q&R requirements and/or other
specifications are being met. If Intel determines that
requirements are not being met, Intel shall notify ChipPAC and
Intel may reject any affected Intel Product and the affected lots
and return it to ChipPAC. If ChipPAC is responsible for the
failure and is unable to correct the problem after a reasonable
period of time, Intel may cancel, at no cost or obligation to
Intel, Releases for Intel Products affected by the problem and
Intel shall have no liability for WIP.
(b) If Intel Product fails to consistently meet the Q&R requirements,
or if in Intel's reasonable opinion, any failure or recurring
failure by ChipPAC to maintain the specifications referenced in
Exhibit B could lead to damage to the reputation of Intel or
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Intel products, the Parties agree that the senior management of
the Parties, within two (2) working days after receipt of a
written notice from Intel of such situation, will commence
discussions regarding the problem. The Parties will cooperate
fully and share all relevant information in attempting to resolve
the situation. If the Parties do not mutually agree after such
discussion that the problems have been resolved, ChipPAC will, at
Intel's written request, cease manufacturing any Intel Products
which, in Intel's opinion, may be affected by such reliability,
quality or process control problems until such time as Intel
agrees that the problem or problems have been resolved. Further,
if ChipPAC is responsible for the failure or recurring failure,
then Intel may cancel Intel Product orders at no cost or
obligation to Intel, including for WIP.
9.9 Audit. Intel representatives and key customer representatives, upon
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Intel's request, shall be allowed to visit ChipPAC's assembly and test
facilities during normal working hours upon reasonable notice to
ChipPAC for the purpose of monitoring production processes and
compliance with any requirements set forth in this Agreement. Upon
completion of the audit, ChipPAC and Intel will mutually agree to an
audit closure plan, to be documented in the audit report issued by
Intel. ChipPAC agrees to execute the audit closure plan within
ninety (90) days of receipt of the audit report.
10. PACKING AND SHIPMENT
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10.1 ChipPAC shall mark and pack all Intel Product in accordance with the
specifications referenced in Exhibit B.
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10.2 Transportation charges and insurance for all returned Intel Products
and Rejects are to be paid by ChipPAC. Risk of loss for Intel
Products and all returned Rejects in transit shall remain with
ChipPAC. This paragraph shall not apply in cases where Intel uses a
designated freight forwarder for Intel Products and Rejects.
-11-
10.3 F.O.B. point for Intel Product is point of origin unless otherwise
specified by Intel and agreed to by both Parties. All items shall be
prepared for shipment in a manner which (i) follows good commercial
practice, (ii) is acceptable to common carriers for shipment at the
lowest rate, and (iii) is adequate to ensure safe arrival. ChipPAC
shall mark all containers with necessary lifting, handling and
shipping information, purchase order number, and the date of
shipment. ChipPAC shall select the most cost effective carrier, given
the time constraints known to ChipPAC. This paragraph shall not apply
in cases where Intel uses a designated freight forwarder or provides
ChipPAC with other written instructions for Intel Products and
Rejects.
10.4 ChipPAC may use any freight forwarder of its own designation for
Rejects being returned under warranty as specified in Section 11
below, in which case, ChipPAC shall make all transportation
arrangements and prepay charges of transportation between Intel and
ChipPAC.
11. WARRANTY
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11.1 ChipPAC warrants that the Services for Intel Products performed by
ChipPAC shall be free from defects in material and workmanship, shall
not affect the merchantability of Intel Products for so long as such
Intel Products are used by any means fit for ordinary purposes, and
shall meet all agreed upon specifications and requirements as stated
in Section 2, Exhibits A and B. Intel may reject and immediately stop
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shipment of Intel Product which fails to meet the foregoing warranty.
If ChipPAC is unable to correct such failure within a reasonable
time, Intel may cancel, at no cost or obligation to Intel, Releases
subject to the failure, and Intel shall have no obligation for WIP.
If such failure continues or affects a significant amount of Product,
Intel may terminate this Agreement.
11.2 Claims. Intel Product subject to warranty claims shall be returned to
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ChipPAC together with an explanation of claim. Intel shall not make a
claim under this warranty no more than eighteen (18) months after
Intel Product delivery. ChipPAC shall replace any Rejects covered by
the warranty with replacement Intel Products in equivalent number and
within the appropriate Leadtime as specified on Exhibit F, without
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charge to Intel and with ChipPAC paying Intel the amount listed in
Exhibit F (liquidated damages assessment) for each replacement Die
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Product. Intel has the option to trade the current package
replacement with a different Intel Product as Intel demand indicates.
11.3 Intel may, at its option, perform an incoming Intel Product
inspection within sixty (60) days of Intel's receipt of Intel
Product. Intel shall notify ChipPAC in writing that it will be
returning Rejects to ChipPAC for verification. ChipPAC shall verify
that the Intel rejection was appropriate within two (2) weeks after
receipt. If Intel does not send notification to ChipPAC that Rejects
will be returned, then it is agreed that the
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Intel Products subject to the then current shipment is deemed to have
passed quality inspection and the warranty period begins to run.
11.4 Rejection Criteria
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(a) If any full or partial shipment of Intel Product delivered to
Intel fail to comply with this warranty, then at its option,
Intel may: i) reject defective Intel Product and return them to
ChipPAC for rework, or ii) in the event rework is not possible,
Intel may within one-hundred-twenty (120) days from date of
rejection, furnish to ChipPAC sufficient additional Wafers or
Die Product to permit ChipPAC to provide replacement of Intel
Product at no cost to Intel, or iii) reject the work on any or
all Rejects and not pay for such work.
(b) All labor and shipping for reworked and replacement Intel
Products shall be provided by ChipPAC at no additional charge to
Intel so long as the assembly requirements for the Intel Product
being reworked or replaced have not changed since the original
labor was provided.
(c) All rework and replacement Intel Product shall be completed and
returned to Intel within the maximum TPT (as specified in
Exhibit C) from the date of receipt by ChipPAC, unless otherwise
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agreed to in writing by both Parties.
11.5 CHIPPAC'S EXPRESS WARRANTIES INCLUDING THE WARRANTY OF
MERCHANTABILITY SET FORTH IN THIS AGREEMENT ARE IN LIEU OF ALL OTHER
WARRANTIES OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING WITHOUT
LIMITATION, WARRANTIES AS TO CONDITION, DESCRIPTION, FITNESS FOR A
PARTICULAR PURPOSE, INFRINGEMENT, OR AS TO ANY OTHER MATTER.
11.6 Return of Wafers and Die Product; Liquidated Damages; and Accounting
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(a) Return of Wafers and Die Product. Unless otherwise agreed,
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ChipPAC hereby acknowledges and agrees it is responsible to
Intel for the return of all Wafers and Die Product delivered to
ChipPAC by Intel; the Wafers and Die Product may be returned as
Intel Product or otherwise. Any Intel Product not meeting the
specifications contained in Exhibit A shall be returned to Intel
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as Rejects (separated and labeled accordingly).
(b) Liquidated Damages. The failure of ChipPAC to return any Wafers
------------------
and Die Products to Intel, as either Wafers or Die Product, Intel
Product, Pre-Production Parts or Rejects, expressed as a yield
percentage of the total amount of good Die Products supplied by
Intel, as shown on Exhibit F, shall subject ChipPac to a
---------
liquidated damage assessment as specified on Exhibit F.
---------
-13-
Such damages shall be assessed as liquidated damages and not as a
penalty, as it would be difficult or impossible to ascertain
Intel's actual damages. In addition, Intel shall not pay any
packaging costs or unacceptable, damaged or lost Die product. At
Intel's option, liquidated damages may be offset against monies
owed to ChipPAC by Intel.
(c) Accounting. Wafers and Die Product shall be reconciled with any
----------
variances dispositioned on a monthly basis, on a report provided
by ChipPAC within one (1) week following each Intel month end as
shown by the calendar in Exhibit G. ChipPAC shall also provide a
---------
detailed explanation of the reason(s) for any failure or
inability to return delivered Wafers and Die Product. This
accounting is supplemental to the reports specified in Section
7.2 and subject to Intel's audit rights specified in Section 9.9.
11.7 RMA Procedures. All Rejects or Finished Products returned to ChipPAC
--------------
by Intel, under this Section 11, shall be in accordance with ChipPAC's
Return Material Authorization ("RMA") set forth in Exhibit H. ChipPAC
---------
shall pay all freight charges on returned materials.
12. INSURANCE
---------
12.1 ChipPAC shall bear all risk of loss for all Intel Product, WIP, Pre-
Production Parts, Rejects, Wafer and Die Product while at its
Facility, including providing at its own expense, adequate Commercial
Property Insurance or Inland Marine Insurance against loss of or
damage to the Wafer and Die Product which shall cover, as a minimum,
the replacement cost of all the Wafer and Die Product provided by
Intel, with Intel named as a Loss Payee. ChipPAC shall bear the cost
of any deductible or co-insurance. In the event of loss or damage,
ChipPAC shall promptly reimburse Intel for all replacement costs,
including all such deductible or co-insurance costs.
12.2 Without limiting or qualifying ChipPAC's liabilities, obligations, or
indemnities otherwise assumed by ChipPAC pursuant to this Agreement,
ChipPAC shall maintain, at its sole cost and expense with companies
acceptable to Intel, Commercial General Liability and Automotive
Liability Insurance with limits of liability not less than $1,000,000
per occurrence and including liability coverage for bodily injury or
property damage (i) assumed in a contract or agreement pertaining to
ChipPAC's business, and (ii) arising out of ChipPAC's Services.
ChipPAC's insurance shall be primary and any applicable insurance
maintained by Intel shall be excess and non-contributing. The above
coverage shall name Intel as an additional insured, and shall contain
a severability of interest clause.
12.3 ChipPAC shall also maintain Statutory Workers' Compensation coverage,
including a Broad Form All States endorsement in the amount required
by law, and Employer's
-14-
Liability insurance coverage with liability limits of not less than
$1,000,000 per occurrence. Such insurance shall include an insurer's
waiver of subrogation in favor of Intel.
12.4 ChipPAC shall provide Intel with properly executed Certificates of
Insurance prior to furnishing any Intel Product or Services hereunder
and shall notify Intel, no less than thirty (30) days in advance of
any reduction or cancellation of the above coverage.
12.5 Notwithstanding the insurance requirements of this Agreement, ChipPAC
shall be given the option to self insure for so long as ChipPAC's net
worth as a corporate entity remains above one billion dollars
($1,000,000,000). Coverage shall apply to any loss which but for the
existence of a deductible or self-insured retention would be covered
under the insurance requirements described herein.
13. LIMITATION OF LIABILITY
-----------------------
13.1 IN NO EVENT SHALL EITHER PARTY BE LIABLE UNDER THIS AGREEMENT FOR LOSS
OF PROFITS, LOSS OF DATA OR USE, OR ANY SPECIAL, CONSEQUENTIAL OR
INCIDENTAL DAMAGES, HOWEVER CAUSED, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. IN NO EVENT WILL EITHER PARTY'S LIABILITY TO THE OTHER
EXCEED THE SUMS PAID BY INTEL TO CHIPPAC UNDER THIS AGREEMENT. THE
PARTIES ACKNOWLEDGE THAT THESE LIMITATIONS ON POTENTIAL LIABILITIES
ARE AN ESSENTIAL ELEMENT IN SETTING CONSIDERATION UNDER THIS
AGREEMENT.
14. INDEMNIFICATION
---------------
14.1 ChipPAC agrees to defend, indemnify and hold Intel harmless from and
against any and all claims, liability, demands, suits, forfeitures,
penalties, judgment, and the associated costs and expenses (including
attorney's fees), which it may hereafter incur, become responsible for
or payout as a result of death or personal injury (including bodily
injury) to any person, destruction or damage to any property,
contamination of or adverse affects on the environment and any clean-
up costs in connection therewith, or any violation of law,
governmental regulation or orders, caused in whole or in part by i)
ChipPAC's breach of any term or provision of this Agreement, or ii)
any acts, errors or omissions by ChipPAC, its employees, officers,
agents, representatives, or sub-contractors of any terms or provision
of this Agreement, or iii) Services or Piece Parts provided by
ChipPAC.
14.2 Intellectual Property Indemnification. ChipPAC shall defend,
-------------------------------------
indemnify, and hold Intel and its customers harmless from any costs,
expenses (including attorney's fees), losses, damages or liability
incurred because of actual or alleged infringement of any
-15-
patent, copyright, trade secret, trademark, maskwork or other
proprietary right arising out of the use or sale by Intel or use by
Intel's customers of Intel Product. Intel shall notify ChipPAC of such
claim or demand and shall permit ChipPAC to participate in the defense
hereof. If an injunction issues as a result of any such claim, ChipPAC
agrees at its expense and Intel's option to either (i) procure for
Intel the right to continue using Intel Product, (ii) replace them
with non-infringing Intel Product, (iii) modify them so they become
non-infringing, or (iv) refund to Intel the amount paid. Such
indemnification shall not apply where items are manufactured to
Intel's detailed design.
15. TERM AND TERMINATION
--------------------
15.1 This Agreement shall become effective only upon the consummation of
the recapitalization transactions contemplated by that certain
Agreement and Plan of Recapitalization and Merger dated as of March
13, 1999, as amended, by and among Hyundai Electronics Industries Co.,
Ltd., Hyundai Electronics America, ChipPAC, Inc. and ChipPAC Merger
Corp., and shall be of no force or effect prior to such time. This
Agreement shall have prospective effect from the consummation of such
recapitalization transactions only and shall have no retroactive
effect to any time prior to the consummation of such recapitalization
transactions. This Agreement shall forthwith lapse if the
Recapitalization Agreement is terminated. This Agreement shall remain
in effect until 30 months after July 1, 1999, unless extended by
mutual agreement of the parties.
15.2 Termination by Intel for Cause. Notwithstanding anything in Paragraph
------------------------------
15.1 to the contrary, if ChipPAC fails to meet Intel's quality
standards, specifications, rejection rates or yield rates as specified
in Exhibits B and C, or any other material breach of this Agreement,
----------------
then Intel may give ChipPAC sixty (60) days written notice of
intention to terminate this Agreement. If ChipPAC has not corrected
such deficiencies as specified by Intel within said sixty (60) day
period, then Intel may terminate this Agreement by written notice at
the end of said sixty (60) day period.
15.3 Termination by ChipPAC for Cause. Notwithstanding anything in
--------------------------------
Paragraph 15.1 to the contrary, if Intel has committed a material
breach of this Agreement, then ChipPAC may give Intel sixty (60) days
written notice of intention to terminate this Agreement. If Intel has
not corrected such deficiencies as specified by ChipPAC within said
sixty (60) day period, then ChipPAC may terminate this Agreement by
written notice at the end of said sixty (60) day period.
15.4 Termination by Mutual Agreement. In addition to the parties'
-------------------------------
respective rights above, this Agreement may be terminated by mutual
written agreement by and between ChipPAC and Intel.
-16-
15.5 Technology Transfer. For purpose of this section, a "transfer event"
-------------------
shall include the following: (i) ChipPAC is unable to meet its
delivery commitments; (ii) ChipPAC materially breaches the Agreement
and/or (iii) when volume requires that Intel or other second source
manufacturing capacity be established to meet Intel's requirements. If
transfer event occurs, Intel shall notify ChipPAC. The Parties agree
that ChipPAC shall provide to Intel, the manufacturing process
database, test tape, assembly design rules and other intellectual
property specific to the affected Intel Product(s) necessary to bring
up an alternative manufacturing source (whether with a third party or
Intel) for Intel Product. The specific terms, conditions and costs of
the Technology Transfer shall be negotiated in good faith and shall be
mutually agreed upon in writing.
15.6 Obligations Upon Termination
----------------------------
(a) In the event of termination by mutual agreement or termination by
either party for cause, ChipPAC shall, within thirty (30) days
from date of termination, provide a certified accounting for and
return to Intel at Intel's cost and expense all Wafers, Die
Product, Intel Product, Pre-Production Parts, WIP, Rejects,
specifications, documentation, Intel developed software, and any
other materials provided to ChipPAC by Intel during the term of
this Agreement.
(b) If ChipPAC does not return said Wafers, Die Product, Intel
Product, Pre-Production Parts, WIP, or other materials provided
by Intel within such thirty (30) day period, Intel shall invoice
ChipPAC and ChipPAC shall pay Intel an amount equal to Intel's
list price or purchase price or, if neither is available, the
replacement costs for all non-returned materials.
(c) Intel shall have no obligations upon termination except to pay
any outstanding invoices for Intel Product ordered by Intel and
produced by ChipPAC or for WIP based upon the agreed upon
cancellation charges for each Intel Product, as a result of Intel
orders placed prior to the termination notice.
(d) Intel's rights and remedies herein are in addition to any other
rights and remedies provided by law or in equity.
(e) There shall be no charges for termination of orders for Services
not yet provided. Intel shall be responsible for payment of
authorized Services already provided by ChipPAC but not yet
invoiced.
(f) Before assuming any payment obligation under this Section, Intel
may inspect ChipPAC's work and audit all relevant documents.
-17-
15.7 Continuing Rights and Obligations. The respective rights and
---------------------------------
obligations of ChipPAC and Intel under the provisions of Section 4
OWNERSHIP, Section 5 CONFIDENTIALITY AND PUBLICITY, Section 11
WARRANTY, Section 13 LIMITATION OF LIABILITY, Section 14
INDEMNIFICATION, Paragraph 18.1 Controlling Law, and Section 19
Dispute Resolution shall survive termination of this Agreement.
16. HAZARDOUS MATERIALS
-------------------
16.1 If Intel Product, Rejects or Services include hazardous materials as
defined by relevant local, state and national law, ChipPAC represents
and warrants that ChipPAC and its personnel providing Services and
Piece Parts to Intel understand the nature of and hazards associated
with the design and/or service of items including handling,
transportation, and use of such hazardous materials, as applicable to
ChipPAC. Prior to causing hazardous materials to be on Intel's
property, ChipPAC shall obtain written approval from Intel's site
Environmental/Health/Safety organization. ChipPAC shall be fully
responsible for indemnification to Intel for any liability resulting
from ChipPAC's actions in connection with (i) providing such hazardous
materials to Intel, or (ii) the use of such hazardous materials in
providing Intel Product, Rejects, Piece Parts or Services to Intel.
The foregoing indemnification and liability shall not be applied to
the actions or measures taken by ChipPAC pursuant to the express
written instructions of Intel where ChipPAC has stated reasonable
objection.
16.2 As they become available, ChipPAC shall provide Intel with material
safety data sheets and any other documentation reasonably necessary to
enable Intel to comply with applicable laws and regulations.
16.3 ChipPAC hereby certifies that Intel Product or Piece Parts supplied to
Intel do not contain and are not manufactured with any ozone depleting
substances, as those terms are defined by law.
17. NEW DEVELOPMENTS
----------------
17.1 All inventions and discoveries, whether or not patentable, made by
Intel employee(s) in the course of performance of this Agreement not
using the confidential information of ChipPAC shall be the sole and
exclusive property of Intel, and Intel shall retain any and all rights
to file at its sole discretion any patent application thereon.
17.2 All inventions and discoveries, whether or not patentable, made by
ChipPAC employee(s) in the course of performance of this Agreement not
using the Confidential Information of Intel shall be the sole and
exclusive property of ChipPAC, and ChipPAC shall retain any and all
rights to file at its sole discretion any patent application thereon.
-18-
17.3 If Intel and ChipPAC jointly made inventions or discoveries, whether
or not patentable, not using the confidential information of either
Intel or ChipPAC, in the course of performance of this Agreement, then
unless provided herein, such joint invention shall be jointly owned by
Intel and ChipPAC with each party having the right to exploit and
grant licenses in respect to such inventions and any patents arising
therefrom, without the consent of or accounting to the other Party.
In the event of a joint invention, the Parties shall mutually agree
which Party shall have the responsibility for preparing and filing any
patent application on the invention and the Parties agree to execute
documents required for and equitably share in the expenses associated
with obtaining and maintaining such patents.
17.4 In the event one Party elects not to seek or maintain patent
protection for any joint invention in any particular country or not to
share equitably in the expenses thereof with the other Party, that
other Party shall have the right to apply for or maintain such patent
protection at its own expense in such country, and shall have full
control over the protection and maintenance therefor, even though
title and rights to any patent resulting therefrom shall be jointly
owned.
18. GENERAL
-------
18.1 Controlling Law. Any claim arising under or relating to this
---------------
Agreement shall be governed by the internal substantive laws of the
State of Delaware without regard to principles of conflict of laws.
Each party hereby agrees to jurisdiction and venue in the State of
Delaware or federal courts located in Delaware for all disputes and
litigation arising under or relating to this Agreement. This
provision is meant to comply with 6 Del. C. Section 2708(a).
18.2 Compliance With Laws. ChipPAC shall comply with all applicable
--------------------
federal, state and local laws and regulations governing the
maintenance and operation of the Facility and performance of Services
covered by this Agreement, including, but not limited to, Department
of Commerce, Environmental Protection Agency and Department of
Transportation regulations applicable to hazardous materials and all
employment and labor laws governing ChipPAC's personnel providing
Services to Intel.
18.3 Export Control. ChipPAC shall not export, either directly or
--------------
indirectly, any Wafers, Die Product or Intel Product without first
obtaining any required license or other approval from the U.S.
Department of Commerce or any other agency or department of the United
States Government.
18.4 Force Majeure. The Parties hereto shall not be liable for any failure
-------------
to perform due to unforeseen circumstances or causes beyond that
Party's reasonable control. Examples of such causes include, but are
not limited to, acts of God, war, riot,
-19-
embargoes, acts of civil or military authority, fire, flood,
accidents, labor disputes (but no more than one (1) labor dispute
occurrence per year) earthquakes or shortages of transportation
facilities, fuel or materials which cannot be reasonably replaced from
other sources. If the Services are to be delayed by such
contingencies, ChipPAC shall immediately notify Intel in writing and
Intel may either i) extend time of performance, or ii) terminate the
uncompleted portion of the order at no cost to Intel, or iii)
terminate this Agreement under the provisions of Paragraph 15.3. In
cases of a labor dispute ChipPAC shall be responsible to return all
Intel Products, Wafers, Die Product, Rejects, documentation and
related materials to Intel in accordance with Paragraph 15.5 if so
requested by Intel.
18.5 No Partnership/Joint Venture. Performance by the Parties under this
----------------------------
Agreement shall be as independent contractors. Nothing contained
herein or performed under the terms of this Agreement shall constitute
the Parties entering upon a joint venture or partnership, or shall
constitute either Party as the agent of the other Party for any
purpose.
18.6 Assignment. Intel may assign this Agreement to its subsidiaries or
----------
affiliates, authorized distributors, or any successor by merger
without ChipPAC's consent; and ChipPAC may assign this Agreement to
its subsidiaries or affiliates without Intel's consent. Otherwise,
this Agreement may not be assigned or otherwise transferred, in whole
or in part by either Party without the other's prior written consent.
No attempt to assign or to transfer in violation of this provision by
either Party shall be binding upon the other.
18.7 Trademarks. Neither Party has any right to use any trademark, logo,
----------
trade name or other identifying mark of the other Party.
18.8 Waiver. Failure by either Party to insist in any instance upon strict
------
conformance to any term or condition herein, or failure by either
Party to act in the event of a breach or default, shall not be
construed as a consent to or a waiver of that breach or default or any
subsequent breach or default of the same or of any other term or
condition contained herein.
18.9 Notices. Any notice required under this Agreement shall be given in
-------
writing and delivered in person or by certified or first-class United
States mail, properly addressed and stamped with the required postage,
to the intended recipient as follows:
For ChipPAC Limited: For Intel:
-20-
ChipPAC Limited Intel Corporation
Craigmuir Chambers M/S C6-404
Road Town, Tortola 5000 West Chandler Boulevard
British Virgin Islands Chandler, AZ 85226
Attention: Resident Director Attention: Legal Department
cc: cc:
ChipPAC, Inc. Intel Corporation
3151 Coronado Drive M/S SC4-203
Santa Clara, CA 95054, USA 2200 Mission College Blvd.
Attention: Chief Executive Officer Santa Clara, CA 95052
Attention: Legal Department
Either party may change its address as listed above by providing advance
written notice to the other Party.
18.10 Severability. If any provision of this Agreement shall be held to
------------
be invalid, illegal or unenforceable, the validity, legality and
enforceability of the remaining provisions shall not in any way be
affected or impaired thereby.
18.11 Order of Precedence.
-------------------
(a) Orders placed hereunder during the term of this Agreement shall
be governed by and subject to only the terms and conditions of
this Agreement and applicable Releases. If any inconsistency or
conflict should arise between this Agreement and the applicable
Releases, the order of precedence in resolving such
inconsistency or conflict shall be:
(1) Release Instructions;
(2) Amendments to this Agreement;
(3) This Agreement;
(4) Product Specifications; and
(5) Exhibits to this Agreement.
(b) Notwithstanding the foregoing, the Parties agree that the terms
and conditions preprinted on the Releases and/or ChipPAC's
order acknowledgment forms, shall not apply.
-21-
(c) It is expressly agreed that any lack of reference to this
Agreement on any Purchase Order issued by Intel shall not
affect the applicability of this Agreement to such order.
18.12 Entire Agreement. This Agreement, including the recitals and the
----------------
referenced Exhibits, set forth the entire Agreement of the Parties
with respect to the subject matter hereof, and supersedes all prior
and contemporaneous negotiations, correspondence and agreements
pertaining thereto. No modification or waiver of any provision of
this Agreement or consent to any departure therefrom shall be
effective unless made in writing by authorized representatives of
the Parties hereto.
18.13 Ownership and Bailment Responsibilities. Any specifications,
---------------------------------------
drawings, schematics, technical information, data, tools, dies,
patterns, masks, samples, gauges, test equipment and other materials
furnished to ChipPAC or paid for by Intel shall (i) be kept
confidential, (ii) remain or become Intel's property, (iii) be used
by ChipPAC exclusively for Intel's orders, (iv) be clearly marked as
Intel's property, (v) be segregated when not in use, (vi) be kept in
good working condition at ChipPAC's expense, and (vii) be shipped to
Intel promptly on Intel's demand or upon termination or expiration
of this Agreement, whichever occurs first.
ChipPAC shall adequately insure Intel's property. ChipPAC shall be
liable for loss or damage to Intel's property while in ChipPAC's
possession or control.
19. DISPUTE RESOLUTION
------------------
19.1 All disputes arising directly under the express terms of this
Agreement or the grounds for termination thereof shall be resolved
as follows:
The senior management of both Parties shall meet to attempt to
resolve such disputes. If the disputes cannot be resolved by the
senior management, either Party may make a written demand for formal
dispute resolution and specify therein the scope of the dispute.
Within thirty (30) days after such written notification, the Parties
agree to meet for one day with an impartial mediator and consider
dispute resolution alternatives other than litigation. If an
alternative method of dispute resolution is not agreed upon within
thirty (30) days after the one (1) day mediation, either Party may
begin litigation proceedings.
20. EXHIBITS
--------
The following Exhibits are included as part of this Agreement:
Exhibit A - Services Requirements
-22-
Exhibit B - Specifications/Performance Standards
Exhibit C - Yields/TPT/LIPAS
Exhibit D - Intel Wafer and Die Product Provided to ChipPAC
Exhibit E - Contract Pricing/Cancellation Liability
Exhibit F - Liquidated Damages/Replacement Product Leadtime
Exhibit G - Intel Work Week Calendar
Exhibit H - ChipPAC's RMA Procedures
IN WITNESS WHEREOF, the parties hereto have executed this Agreement on the dates
indicated by their respective signatures.
CHIPPAC LIMITED INTEL CORPORATION
By: /s/ Richard Parsons By: /s/ Craig C. Brown
--------------------------------- -------------------------------
Signature Signature
Richard Parsons for Westlaw Limited Craig C. Brown
- ------------------------------------- -----------------------------------
Name Name
Director Director
- ------------------------------------- -----------------------------------
Title Title
July 20, 1999 July 30, 1999
- ------------------------------------- -----------------------------------
Date Date
-23-
EXHIBIT A
SERVICES REQUIREMENTS
---------------------
Intel requires ChipPAC to assemble Intel-provided die in wafer form into
[redacted*] and/or [redacted*] and ship the assembled Intel Product to Intel.
*Confidential treatment requested.
A-1
INTEL CONFIDENTIAL
------------------
EXHIBIT "B"
SPECIFICATIONS/PERFORMANCE STANDARDS
------------------------------------
[redacted*]
*Confidential treatment requested.
INTEL CONFIDENTIAL
------------------
SPECIFICATIONS/PERFORMANCE STANDARDS (Continued)
------------------------------------------------
INTEL CONFIDENTIAL
------------------
SPECIFICATIONS/PERFORMANCE STANDARDS (Continued)
------------------------------------------------
EXHIBIT C
YIELD/TPT/LIPAS
---------------
AVG. AVG. AVG. LINE ITEM
PRODUCT TIME PERIOD YIELDS TPT PERFORMANCE
[redacted*] Effective Date thru [redacted*]% [redacted*] days 100%
Termination of Agreement
[redacted*] Effective Date thru [redacted*]% [redacted*] days 100%
Termination of Agreement
[redacted*] Effective Date thru [redacted*]% [redacted*] days 100%
Termination of Agreement
LIPAS: ChipPAC's LIPAS performance shall be 100%. If ChipPAC's LIPAS
performance falls below 100% for any reason, then ChipPAC shall implement a
corrective action plan approved by Intel to bring deliveries back into 100%
compliance. On-time deliveries for LIPAS performance measurement are defined as
ChipPAC shipping the Intel Product units that are due for that week's delivery
up to [redacted*] days early but [redacted*] days late from the date specified
on the purchase order.
*Confidential treatment requested.
C-1
EXHIBIT D
INTEL WAFERS AND DIE PRODUCT PROVIDED TO CHIPPAC
------------------------------------------------
Intel Products provided to ChipPAC include, but are not limited to, the
following:
Intel die in wafer form with proper thickness which fits ChipPAC's tape
mount and die saw process for the following packages:
[redacted*]
*Confidential treatment requested.
D-1
EXHIBIT E
CONTRACT PRICING REV. 1/CANCELLATION LIABILITY
----------------------------------------------
CONTRACT PRICING
- ----------------
[REDACTED*]
All subsequent pricing changes for all Intel Products are to be mutually agreed
upon between Intel and ChipPAC. Such pricing previsions shall be provided to
Intel by the ChipPAC Strategic Accounts Manager on a timely basis.
*Confidential treatment requested.
E-1
EXHIBIT F
LIQUIDATED DAMAGES & REPLACEMENT PRODUCT LEADTIME
-------------------------------------------------
[REDACTED*]
*Confidential treatment requested.
F-1
INTEL CONFIDENTIAL
EXHIBIT "G"
INTEL WORK WEEK CALENDAR - 1995
-------------------------------
(WW) SUN MON TUES WED THUR FRI SAT
- ------------------------------------------------------------
JANUARY
(01) 31 (1) 2 3 4 5 6
(02) 7 8 9 10 11 12 13
(03) 14 15 16 17 18 19 20
(04) 21 22 23 24 25 26 27
- ------------------------------------------------------------
FEBRUARY
(05) 28 29 30 31 1 2 3
(06) 4 5 6 7 8 9 10
(07) 11 12 13 14 15 16 17
(08) 18 (19) 20 21 22 23 24
- ------------------------------------------------------------
MARCH
(09) 25 26 27 28 29 1 2
(10) 3 4 5 6 7 8 9
(11) 10 11 12 13 14 15 16
(12) 17 18 19 20 21 22 23
(13) 24 25 26 27 28 29 30
- ------------------------------------------------------------
APRIL
(14) 31 1 2 3 4 5 6
(15) 7 8 9 10 11 12 13
(16) 14 15 16 17 18 19 20
(17) 21 22 23 24 25 26 27
- ------------------------------------------------------------
MAY
(18) 28 29 30 1 2 3 4
(19) 5 6 7 8 9 10 11
(20) 12 13 14 15 16 17 18
(21) 19 20 21 22 23 24 25
- ------------------------------------------------------------
JUNE
(22) 26 (27) 28 29 30 31 1
(23) 2 3 4 5 6 7 8
(24) 9 10 11 12 13 14 15
(25) 16 17 18 19 20 21 22
(26) 23 24 25 26 27 28 29
- ------------------------------------------------------------
() = U.S. HOLIDAYS
(WW) SUN MON TUES WED THUR FRI SAT
- ------------------------------------------------------------
JULY
(27) 30 1 2 3 (4) (5) 6
(28) 7 8 9 10 11 12 13
(29) 14 15 16 17 18 19 20
(30) 21 22 23 24 25 26 27
- ------------------------------------------------------------
AUGUST
(31) 28 29 30 21 1 2 3
(32) 4 5 6 7 8 9 10
(33) 11 12 13 14 15 16 17
(34) 18 19 20 21 22 23 24
- ------------------------------------------------------------
SEPTEMBER
(35) 25 26 27 28 29 30 31
(36) 1 (2) 3 4 5 6 7
(37) 8 9 10 11 12 13 14
(38) 15 16 17 18 19 20 21
(39) 22 23 24 25 26 27 28
- ------------------------------------------------------------
OCTOBER
(40) 29 30 1 2 3 4 5
(41) 6 7 8 9 10 11 12
(42) 13 14 15 16 17 18 19
(43) 20 21 22 23 24 25 26
- ------------------------------------------------------------
NOVEMBER
(44) 27 28 29 30 31 1 2
(45) 3 4 5 6 7 8 9
(46) 10 11 12 13 14 15 16
(47) 17 18 19 20 21 22 23
- ------------------------------------------------------------
DECEMBER
(48) 24 25 26 27 (28) (29) 30
(49) 1 2 3 4 5 6 7
(50) 8 9 10 11 12 13 14
(51) 15 16 17 18 19 20 21
(52) 22 23 24 (25) 26 27 28
- ------------------------------------------------------------
*Confidential treatment requested.
EXHIBIT H
CHIPPAC'S RMA PROCEDURES
-------------------------
(SEE ATTACHED CHIPPAC'S RMA PROCEDURES)
H-1
(PROCEDURE GENERATION/REVISION HISTORY SHEET)
(COVER PAGE IN KOREAN)
[LOGO]
- -----------------------------------------------------------------------------
(SCOPE) (TITLE) CPKR-CQ16 REV.
9
- -------------- -------------------
(ChipPAC Korea Co., Ltd.) Return Material Handling PAGE
Procedure 1 OF 8
- -----------------------------------------------------------------------------
(Contents)
(General Rules)
(Purpose)
(Scope)
(Definition)
(Organization)
(Customer Service/Sales Department)
(QA Department)
(Production Depatment)
(P.C Department)
(Logistics Team)
(Procedure)
(Reception)
(Verification)
(Scrap or Rework)
(Record Retention)
- -------------------------------------------------------------------------------
(PREPRATION DEPT) (EFFECTIVE DATE)
- -------------------------------------------------------------------------------
- -------------------------------------------------------------------------------
(TITLE) PAGE REV.
CPKR-CQ18 Return Material Handling Procedure 2 OF 8 9
- -------------------------------------------------------------------------------
(General Rules)
(Purpose)
The administrative standard defines the procedure of the efficient handling
for the return product from customer.
(Scope)
This administrative standard applies to the rework/rescreen flow or
customer return product by product non-conformance.
(Definition)
1. (Return Product)
Return product is the product which is returned from customer for
rework scrapping due to quality non-conformance.
(Organization)
(Sales: Customer service/Sales Department)
Sales is responsible for belows.
1. Receiving the customer return notice.
2. Notification of the return product status to the related departments.
- -------------------------------------------------------------------------------
(TITLE) PAGE REV.
CPKR-CQ16 Return Material Handling Procedure 3 OF 8 9
- -------------------------------------------------------------------------------
(QA: QA Department)
QA is responsible for belows.
1. Do initial verification for customer return product. But it is not
required if QA engineer confirmed the defect sample before receipt of
return product or customer return is caused by simple external visual
reject.
2. Preparing/sending the sheet of "Rework Plan/Result Report for Customer
Return".
(Prod: Production Department)
Prod is responsible for belows.
1. Moving return product from finished goods store to the production
line.
2. Performing the rework in accordance with the rework procedure or
rework schedule.
3. Fill up the sheet of "Rework Plan/Result Report for Customer Return"
after rework & rescreen and submit it to QA gate along with the
screened lot.
(PC: Production Control Department)
PC is responsible for belows.
1. Issuing the rework schedule attached the sheet of "Rework Plan/Result
Report for Customer Return" after confirming the QA and process
engineer.
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(TITLE) PAGE REV.
CPKR-CQ16 Return Material Handling Procedure 4 OF 8 9
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(LT: Logistics Team)
LT (Logistics team) is responsible for belows.
1. Receiving and storing the return product.
2. Perform actual counting of the returned lot.
3. Notifying receiving status for the return product to related
department.
4. Performing the re-ship the return product according to shipping
request.
(Procedure)
(Reception)
1. Upon receive the return product notice from customer, the Sales shall
inform to LT, PC, QA, Eng'g & Prod.
2. The notice shall be included as follows:
-CUSTOMER:
-PACKAGE/LEAD:
-DEVICE/PARTS:
-LOT NO:
-RETURN Q'TY:
-DEFECT Q'TY:
-DEFECT MODE
-RETURN DATE:
3.
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CPKR-CQ16 (TITLE) PAGE REV.
Return Material Handling Procedure 5 OF 8 9
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When the return product arrives at finished goods store, LT has to
segregate the return product from normal finished goods after counting
actual q'ty and shall attach the return/hold label on the boxes of
return product.
4. LT informs the arrival status of return product to Sales, PC, QA and
relevant departments by E-mail or written information.
10. (Verification)
1. When the LT dept notifies the customer return after customer
clearance, QA engineer shall perform the verification for returned lot
as follows:
(1) (Visual Inspection)
If necessary, the QA engineer shall verify the reject units or
some samples selected randomly from returned lot whether those
are agreed with the customer's information.
(2) If failure analysis is required, responsible engineer request
failure analysis to F/A and then the confirm the result whether
it agreeds with customer's information.
(3) If any disagreement items are found through above verification,
the QA engineer shall report those status to customer through
Sales.
2. QA shall decide the rework & rescreen method with the sheet of "Rework
Plan/Result Report for Customer Return" and inform PC to issue
rework schedule.
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CPKR-CQ16 (TITLE) PAGE REV.
Return Material Handling Procedure 6 OF 8 9
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1. After receipt the rework method from the QA, PC shall issue the rework
schedule.
2. Prod shall transfer the return product from finished good store to the
production line when the rework schedule is approved.
3. Prod shall perform the rework in accordance with rework procedure on
the schedule sheet.
4. Reworked product shall be verified by inspection and test plan.
5. Process eng'r or Prod supervisor shall verify production rework &
rescreen status and then comment his own opinion.
If necessary, he should establish additional action item & then record
it on the sheet of "Rework Plan / Result Report for Customer Return".
6. Prod shall submit the return lot attaching the sheet of "Rework Plan /
Result Report for Customer Return" to QA gate after completion of
rework/rescreen.
7. QA shall verify the sheet of "Rework Plan / Result Report for Customer
Return" and verify customer returned lot in accordance with required
inspection plan.
8. The customer return product without QA verification is not allowed to
ship to customer.
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CPKR-CQ16 (TITLE) PAGE REV.
Return Material Handling Procedure 7 OF 8 9
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1. QA shall keep the "Rework Plan / Result Report for Customer Return"
sheet for minimum 3 years.
1. This procedure is controlled by "Quality Manual (CPKR-CB03)",
1. The Sheet of "Rework Plan / Result Report for Customer Return".
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CPKR-CQ16 (TITLE) PAGE REV.
Return Material Handling Procedure 8 OF 8 9
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ATTACHMENT: The Sheet of "Rework Plan/Result Report for Customer Return".
Rework Plan/Result Report
for Customer Return
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Customer Pkg/LD Device Name Lot number Q'ty Return reason
================================================================================
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(RETURN SAMPLE VERIFICATION):
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(REWORK PLAN):
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No (ITEMS) (REWORK METHOD/SPEC) (s/s) (RESP.) (REACTION PLAN)
================================================================================
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1999, Prepared by QA eng'r
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Approved by QA Manager
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(REWORK DATA):
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Data Summary Reject/Rework Mode details
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Input Q'ty
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Out Q'ty
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Scrap Q'ty
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Rework Q'ty
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1999, Prepared by Product Supr'v
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ENGINEERING COMMENT:
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1999, Prepared by Process Eng'r
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1999, Confirmed by Process QA
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