28912 patents
Page 2 of 1446
Utility
Symmetrical Substrate for Semiconductor Packaging
18 Jan 24
An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided.
Jiun Yi Wu, Chen-Hua Yu
Filed: 31 Jul 23
Utility
Connector and Method for Forming the Same
18 Jan 24
A method includes forming a first connector and a second connector over a first wafer and a second wafer, respectively, in which each of the first and second connectors are formed by forming an opening in a dielectric layer; depositing a first metal layer in the opening, in which the first metal layer has a nano-twinned structure with (111) orientation; and depositing a second metal layer over the first metal layer, the second metal layer and the first metal layer being made of different materials, in which the second metal layer has a nano-twinned structure with (111) orientation; attaching the first wafer to the second wafer, such that that the second metal layer of the first connector on the first wafer is in contact with the second metal layer of the second connector on the second wafer; and performing a thermo-compression process to bond the first and second wafers.
Chih CHEN, Hsiang-Hou TSENG
Filed: 15 Jul 22
Utility
a Metal-insulator-metal Device with Improved Performance
18 Jan 24
Various embodiments of the present disclosure are directed towards an integrated chip (IC).
Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsing-Chih Lin, Kuan-Hua Lin
Filed: 25 Jul 23
Utility
Methods of Fabricating the Same Die Stack Structure and Semiconductor Structure
18 Jan 24
A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided.
Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
Filed: 1 Aug 23
Utility
Semiconductor Structure and Method of Manufacturing Thereof
18 Jan 24
The semiconductor structure includes a first die structure including a first substrate, a first bonding dielectric disposed over the first substrate, and a first bonding pad surrounded by the first bonding dielectric; a second die structure including a second substrate, an isolation member extending into the second substrate, a second bonding dielectric bonded with the first bonding dielectric, and a second bonding pad surrounded by the second bonding dielectric and bonded with the first bonding pad; a dielectric member disposed over the second die structure; a conductive via extending through the dielectric member, the second substrate and the isolation member; and a conductive member disposed over the dielectric member and at least partially in contact with the conductive via, wherein a first interface between the conductive via and the conductive member is substantially coplanar with a second interface between the conductive member and the dielectric member.
HARRY-HAK-LAY CHUANG, WEI-CHENG WU, WEN-TUO HUANG, YU-LING HSU, PAI CHI CHOU, YU-CHUN CHANG, CHUNG-JEN HUANG
Filed: 14 Jul 22
Utility
Semiconductor Device
18 Jan 24
A semiconductor device includes a first transistor disposed over a substrate, a second transistor disposed over the first transistor, and a conductive trace.
Pin-Dai SUE, Tzung-Yo HUNG, Jung-Hsuan CHEN, Ting-Wei CHIANG
Filed: 31 Jul 23
Utility
Integrated Circuit Including Supervia and Method of Making
18 Jan 24
An integrated circuit includes a substrate; and a first conductive line extending parallel to a top surface of the substrate.
Kam-Tou SIO, Wei-Cheng LIN, Jiann-Tyng TZENG
Filed: 21 Jul 23
Utility
Backside Illuminated Image Sensor Device with Shielding Layer and Forming Method
18 Jan 24
An image sensor includes a pixel array, a dielectric layer, a plurality of first conductive shielding regions, and a plurality of second conductive shielding regions.
Volume CHIEN, Su-Hua CHANG, Chia-Yu WEI, Zen-Fong HUANG, Chi-Cherng JENG
Filed: 27 Jul 23
Utility
Seal Ring for Hybrid-bond
18 Jan 24
A structure includes a first die and a second die.
Chih-Chia Hu, Chun-Chiang Kuo, Sen-Bor Jan, Ming-Fa Chen, Hsien-Wei Chen
Filed: 25 Jul 23
Utility
Semiconductor Device and Manufacturing Method Thereof
18 Jan 24
A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.
Li-Zhen YU, Chia-Hao CHANG, Cheng-Chi CHUANG, Yu-Ming LIN, Chih-Hao WANG
Filed: 14 Jul 23
Utility
Upper Conductive Structure Having Multilayer Stack to Decrease Fabrication Costs and Increase Performance
18 Jan 24
Various embodiments of the present disclosure are directed towards an integrated chip.
Tzu-Yu Lin, Yao-Wen Chang, Chia-Wen Zhong, Yen-Liang Lin
Filed: 9 Aug 23
Utility
Semiconductor Device and Manufacturing Method Thereof
18 Jan 24
A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures.
Hsien-Wen WAN, Yi-Ting CHENG, Ming-Hwei HONG, Juei-Nai KWO, Bo-Yu YANG, Yu-Jie HONG
Filed: 14 Jul 23
Utility
Payload Transportation System
18 Jan 24
System and method for cross-fab wafer transportation are provided.
Chieh Hsu, Guancyun Li, Ching-Jung Chang, Chi-Feng Tung
Filed: 31 Mar 23
Utility
Field Effect Transistor with Negative Capacitance Dielectric Structures
18 Jan 24
The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed.
Chansyun David YANG, Keh-Jeng CHANG, Chan-Lon YANG
Filed: 31 Jul 23
Utility
Finfet with Source/drain Regions Comprising an Insulator Layer
18 Jan 24
An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer.
Tzu-Ching Lin, Tuoh Bin Ng
Filed: 8 Aug 23
Utility
Semiconductor Structure and Method for Forming the Same
18 Jan 24
A semiconductor structure is provided, and includes a first fin structure, a second fin structure, and a third fin structure over a substrate.
Yun-Ju FAN, Lin-Yu HUANG, Sheng-Tsung WANG, Huan-Chieh SU, Cheng-Chi CHUANG, Chih-Hao WANG
Filed: 14 Jul 22
Utility
Contact Plug with Impurity Variation
18 Jan 24
A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature.
Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su
Filed: 26 Jul 23
Utility
Semiconductor Device with Tunable Threshold Voltage and Method for Manufacturing the Same
18 Jan 24
A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements.
Chansyun David YANG, Huang-Lin CHAO, Hsiang-Pi CHANG, Yen-Tien TUNG, Chung-Liang CHENG, Yu-Chia LIANG, Shen-Yang LEE, Yao-Sheng HUANG, Tzer-Min SHEN, Pinyen LIN
Filed: 15 Jul 22
Utility
Semiconductor Device and Method
18 Jan 24
Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the of scallops having a first depth, the scallops having a greater depth.
Hsu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng, Chen-En Yen, Cheng-Lung Yang, Kuanchih Huang
Filed: 31 Jul 23
Utility
Signal Generator for Controlling Timing of Signal In Memory Device
18 Jan 24
A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator.
Xiu-Li YANG, He-Zhou WAN, Mu-Yang YE, Lu-Ping KONG, Ming-Hung CHANG
Filed: 27 Sep 23