128 patents
Page 2 of 7
Utility
Multi-protocol frame format
19 Aug 21
Communication apparatus includes a transceiver configured to communicate over a wireless channel in accordance with both a first and a second communication protocol.
Rui Cao, Hongyuan Zhang, Prashant Sharma
Filed: 2 May 21
Utility
Through-Silicon Via for High-Speed Interconnects
29 Jul 21
A device includes a semiconductor substrate having first and second surfaces facing one another, and multiple through-silicon vias (TSVs).
Runzi Chang
Filed: 26 Jan 21
Utility
On-chip Parameter Generation System with an Integrated Calibration Circuit
22 Jul 21
Disclosed are embodiments of an integrated circuit (IC) chip that includes an on-chip parameter generation system.
Eric Hunt-Schroeder, Alexander J. Filmer
Filed: 21 Jan 20
Utility
Interrupt Servicing In Userspace
8 Jul 21
A method for handling an interrupt includes receiving, in hardware or in firmware, a request from a task executing in userspace, where the request is to assign a function in the task and state information for the task to an interrupt.
Alexander BELITS, Prasun KAPOOR
Filed: 8 Jan 20
Utility
Processing Unit and Method for Computing a Convolution Using a Hardware-implemented Spiral Algorithm
24 Jun 21
Disclosed is a processing unit for computing a convolution of an activations matrix (e.g., a N×N activations matrix) and a weights kernel (e.g., a M×M weights kernel).
Deepak I. Hanagandi, Venkatraghavan Bringivijayaraghavan, Aravindan J. Busi
Filed: 23 Dec 19
Utility
Automotive Data Processing System with Efficient Generation and Exporting of Metadata
17 Jun 21
An automotive data processing system includes a storage subsystem and a processor.
Noam Mizrahi
Filed: 8 Dec 20
Utility
Row Address Comparator for a Row Redundancy Control Circuit In a Memory
17 Jun 21
Disclosed is a row address comparator with voltage level shifting and latching functionality and including: an evaluation section for comparing two row addresses in a first voltage domain and outputting an initial match signal in a second voltage domain; and a latch section for outputting a latched final match signal based on the initial match signal.
Venkatraghavan Bringivijayaraghavan, Sreejith Chidambaran, Prasad Vernekar
Filed: 12 Dec 19
Utility
Hybrid Fixed/Programmable Header Parser for Network Devices
17 Jun 21
A packet processor of a network device includes a forwarding engine that is configured to determine egress network interfaces via which packets received by the network device are to be transmitted.
Yaron KITTNER, Ilan YERUSHALMI, Adar PEERY, Aviram AMIR
Filed: 11 Dec 20
Utility
Eliminating Execution of Instructions That Produce a Constant Result
3 Jun 21
An instruction is received by a processing pipeline of a computer processor.
David CARLSON
Filed: 3 Dec 19
Utility
Congestion Avoidance In a Network Switch Device
3 Jun 21
Packets received by a network switch device from upstream network devices, coupled to respective ones of a plurality of ports of the network switch device, are temporarily stored in an internal memory of the network switch device.
Zvi Shmilovici LEIB
Filed: 8 Feb 21
Utility
Flow Monitoring In Network Devices
27 May 21
Flow state information that is stored in a first memory among a plurality of memories for maintaining flow state information at a network device is updated based on packets ingressing the network device.
Yosef KATAN, Rami ZEMACH
Filed: 25 Mar 20
Utility
Ic Chip Package with Dummy Solder Structure Under Corner, and Related Method
29 Apr 21
An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon.
Manish Nayini, Richard S. Graf, Janak G. Patel, Nazmul Habib
Filed: 24 Oct 19
Utility
Multiple Sense Amplifier and Data Path-based Pseudo Dual Port Sram
22 Apr 21
A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier.
Venkatraghavan Bringivijayaraghavan, Arjun Sankar, Sreejith Chidambaran, Igor Arsovski
Filed: 17 Oct 19
Utility
Methods and Apparatus for a Vector Memory Subsystem for Use with a Programmable Mixed-radix Dft/idft Processor
8 Apr 21
A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values.
Yuanbin Guo, Hong Jik Kim
Filed: 16 Dec 20
Utility
Merge Execution Unit for Microinstructions
1 Apr 21
David A. Carlson
Filed: 1 Oct 19
Utility
Methods and Apparatus for Job Scheduling In a Programmable Mixed-radix Dft/idft Processor
1 Apr 21
Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor.
Yuanbin Guo, Hong Jik Kim
Filed: 11 Dec 20
Utility
Methods and Apparatus for Dynamic Acknowledgement List Selection In Detection of Uplink Control Channel Formats
1 Apr 21
Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats.
Yuanbin Guo
Filed: 11 Dec 20
Utility
Methods and Apparatus for Job Scheduling In a Programmable Mixed-radix Dft/idft Processor
25 Mar 21
Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor.
Yuanbin Guo, Hong Jik Kim
Filed: 9 Dec 20
Utility
Method of Improving L1 Icache Performance with Large Programs
18 Mar 21
The hit rate of a L1 icache when operating with large programs is substantially improved by reserving a section of the L1 icache for regular instructions and a section for non-instruction information.
Edward MCLELLAN, Alexander RUCKER, Shay GAL-ON, Srilatha MANNE
Filed: 12 Sep 19
Utility
Congestion Notification Packet Indicating Specific Packet Flow Experiencing Congestion to Facilitate Individual Packet Flow Based Transmission Rate Control
18 Mar 21
A system includes first, second, and third processors.
Zvi Leib SHMILOVICI, Gideon Navon
Filed: 9 Nov 20