943 patents
Utility
Dual thickness fuse structures
5 Sep 23
The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture.
John J. Pekarik, Anthony K. Stamper, Vibhor Jain
Filed: 13 Nov 20
Utility
Scaled gate contact and source/drain cap
31 Jan 23
The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture.
Hui Zang, Ruilong Xie, Jae Gon Lee
Filed: 13 Nov 20
Utility
Low resistance source drain contact formation with trench metastable alloys and laser annealing
24 Jan 23
Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided.
Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita, Chun-Chen Yeh
Filed: 1 Feb 19
Utility
Coupling inductors in an IC device using interconnecting elements with solder caps and resulting devices
17 Jan 23
Methods of coupling inductors in an IC device using interconnecting elements with solder caps and the resulting device are disclosed.
Tak Ming Mak, Ajit M. Dubey
Filed: 13 Feb 17
Utility
High-voltage devices integrated on semiconductor-on-insulator substrate
10 Jan 23
The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same.
Ruchil Kumar Jain, Alban Zaka
Filed: 17 May 20
Utility
Bulk substrates with a self-aligned buried polycrystalline layer
13 Dec 22
Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures.
Steven M. Shank, Anthony K. Stamper, Ian McCallum-Cook, Siva P. Adusumilli
Filed: 2 Nov 20
Utility
Diode structures
22 Nov 22
The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture.
Jagar Singh, Shiv Kumar Mishra
Filed: 13 Nov 20
Utility
Methods, Apparatus, and Manufacturing System for Self-aligned Patterning of a Vertical Transistor
28 Jul 22
A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process.
Chanro Park, Ruilong Xie, Min Gyu Sung
Filed: 18 Apr 22
Utility
Metal on metal multiple patterning
26 Jul 22
The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.
Hsueh-Chung Chen, Ravi P. Srivastava, Somnath Ghosh, Nicholas V. Licausi, Terry A. Spooner, Sean Reidy
Filed: 17 Sep 20
Utility
Tight pitch wirings and capacitor(s)
5 Jul 22
The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture.
Anthony K. Stamper, Daisy A. Vaughn, Stephen R. Bosley, Zhong-Xiang He
Filed: 11 Dec 20
Utility
Multiband Receivers for Millimeter Wave Devices
23 Jun 22
We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption.
Abdellatif Bellaouar, Sher Jiun Fang, Frank Zhang
Filed: 20 Dec 21
Utility
Methods, apparatus, and manufacturing system for self-aligned patterning of a vertical transistor
19 Apr 22
A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process.
Chanro Park, Ruilong Xie, Min Gyu Sung
Filed: 14 Aug 17
Utility
Public-private Encryption Key Generation Using Pcell Parameter Values and On-chip Physically Unclonable Function Values
17 Mar 22
Methods and systems generate seeds for public-private key pairs by determining a timestamp value associated with a process design kit (PDK) when a user of the PDK triggers a tool of the PDK while designing an integrated circuit device to have a physical unclonable function device (PUF).
Romain H. A. Feuillette, David C. Pritchard, Bernhard J. Wunder, Elizabeth Strehlow
Filed: 15 Sep 20
Utility
Multiple fin finFET with low-resistance gate structure
1 Mar 22
Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure.
Guillaume Bouche, Andy Chih-Hung Wei
Filed: 26 May 20
Utility
Multiband receivers for millimeter wave devices
18 Jan 22
We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption.
Abdellatif Bellaouar, Sher Jiun Fang, Frank Zhang
Filed: 30 Mar 20
Utility
Method, apparatus and system for wide metal line for SADP routing
21 Dec 21
At least one method, apparatus and system disclosed involves a circuit layout for an integrated circuit device comprising a plurality of wider-than-default metal formations for a functional cell.
Lei Yuan, Juhan Kim
Filed: 14 Oct 20
Utility
Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor
14 Dec 21
A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type.
Ruilong Xie, Steven Soss, Steven Bentley, Daniel Chanemougame, Julien Frougier, Bipul Paul, Lars Liebmann
Filed: 20 Apr 18
Utility
High-voltage Devices Integrated on Semiconductor-on-insulator Substrate
18 Nov 21
The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same.
RUCHIL KUMAR JAIN, ALBAN ZAKA
Filed: 17 May 20
Utility
Multi-channel power combiner with phase adjustment
7 Sep 21
Power combiners having increased output power, such as may be useful in millimeter-wave devices.
See Taur Lee, Sher Jiung Fang, Abdellatif Bellaouar
Filed: 31 Mar 20
Utility
Sensing circuits for charge trap transistors
24 Aug 21
The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.
Eric D. Hunt-Schroeder, Sebastian T. Ventrone, James A. Svarczkopf, Igor Arsovski
Filed: 12 Sep 19