2587 patents
Page 5 of 130
Utility
Method and Apparatus for Recovering Regular Access Performance In Fine-grained Dram
28 Dec 23
A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit.
Sriseshan Srikanth, Vignesh Adhinarayanan, Jagadish B. Kotra, Sergey Blagodurov
Filed: 31 Aug 23
Utility
Binning Pass with Hierarchical Depth Data Determination
28 Dec 23
Currently with performing a visibility pass for two or more coarse bins of an image, a processing system determines a bounding box for a primitive to be rendered for the image based on a bottom left-most point of the primitive and a top right-most point of the primitive.
Kiia K. Kallio, Miikka Kangasluoma, Jan Achrenius
Filed: 28 Jun 22
Utility
Method and Apparatus for Training Memory
21 Dec 23
A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer.
Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani, Tsun Ho Liu
Filed: 21 Jun 22
Utility
Approach for Processing Near-memory Processing Commands Using Near-memory Register Definition Data
21 Dec 23
An approach is provided for processing near-memory processing commands, e.g., PIM commands, using PIM register definition data that defines multiple combinations of source and/or destination registers to be used to process PIM commands.
Shaizeen Aga, Nuwan Jayasena
Filed: 21 Jun 22
Utility
VLIW Dynamic Communication
21 Dec 23
In accordance with described techniques for VLIW Dynamic Communication, an instruction that causes dynamic communication of data to at least one processing element of a very long instruction word (VLIW) machine is dispatched to a plurality of processing elements of the VLIW machine.
Sriseshan Srikanth, Karthik Ramu Sangaiah, Anthony Thomas Gutierrez, Vedula Venkata Srikant Bharadwaj, John Kalamatianos
Filed: 17 Jun 22
Utility
Partial Sorting for Coherency Recovery
21 Dec 23
Devices and methods for partial sorting for coherence recovery are provided.
Matthäus G. Chajdas, Christopher J. Brennan
Filed: 21 Jun 22
Utility
Neural Network Activation Scaled Clipping Layer
21 Dec 23
Activation scaled clipping layers for neural networks are described.
Hai Xiao, Adam H Li, Harris Eleftherios Gasparakis
Filed: 20 Jun 22
Utility
Balanced Throughput of Replicated Partitions In Presence of Inoperable Computational Units
21 Dec 23
An apparatus and method for efficiently managing balanced performance among replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects.
Ashish Jain, Sriram Sundaram, Christopher Allan Poirier, Samuel D. Naffziger
Filed: 20 Jun 22
Utility
Artificial Neural Network Emulation of Hotspots
21 Dec 23
Methods, devices, and systems for emulating a compute kernel with an ANN.
Nicholas Malaya
Filed: 25 Aug 23
Utility
Host-level Error Detection and Fault Correction
21 Dec 23
A processing system includes a processing device coupled to a memory configured to check for and correct faults in requested data.
Sudhanva Gurumurthi, Vilas Sridharan
Filed: 16 Jun 22
Utility
Adaptive Digital Content Preprocessing based on Bitrate
21 Dec 23
Adaptive digital content preprocessing techniques based on a bitrate are described.
Marvin Younan, Ihab Amer, Feng Pan
Filed: 21 Jun 22
Utility
Volume Intersection Using Rotated Bounding Volumes
21 Dec 23
One or more rotated bounding volumes are generated for one or more nodes of a bounding volume hierarchy (BVH).
Miikka Kangasluoma, Kiia Kallio, Daniel James Skinner
Filed: 17 Jun 22
Utility
High-speed Die Connections Using a Conductive Insert
21 Dec 23
A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.
RAHUL AGARWAL
Filed: 25 Aug 23
Utility
Method and apparatus for providing persistence to remote non-volatile memory
19 Dec 23
A processing device and methods of controlling remote persistent writes are provided.
Nuwan Jayasena, Shaizeen Aga
Filed: 24 Sep 20
Utility
Approach for reducing side effects of computation offload to memory
19 Dec 23
A technical solution to the technical problem of how to reduce the undesirable side effects of offloading computations to memory uses read hints to preload results of memory-side processing into a processor-side cache.
Shaizeen Aga, Nuwan Jayasena
Filed: 30 Jun 21
Utility
Approach for supporting memory-centric operations on cached data
19 Dec 23
A technical solution to the technical problem of how to support memory-centric operations on cached data uses a novel memory-centric memory operation that invokes write back functionality on cache controllers and memory controllers.
Shaizeen Aga, Nuwan Jayasena, John Kalamatianos
Filed: 26 Jul 21
Utility
Re-fetching data for L3 cache data evictions into a last-level cache
19 Dec 23
In response to eviction of a first clean data block from an intermediate level of cache in a multi-cache hierarchy of a processing system, a cache controller accesses an address of the first clean data block.
Tarun Nakra, Jay Fleischman, Gautam Tarasingh Hazari, Akhil Arunkumar, William L. Walker, Gabriel H. Loh, John Kalamatianos, Marko Scrbak
Filed: 16 Dec 21
Utility
Software-based instruction scoreboard for arithmetic logic units
19 Dec 23
A software-based instruction scoreboard indicates dependencies between closely-issued instructions issued to an arithmetic logic unit (ALU) pipeline.
Brian Emberling
Filed: 15 Dec 20
Utility
Masked multi-lane instruction memory fault handling using fast and slow execution paths
19 Dec 23
A processor includes a load/store unit and an execution pipeline to execute an instruction that represents a single-instruction-multiple-data (SIMD) operation, and which references a memory block storing operand data for one or more lanes of a plurality of lanes and a mask vector indicating which lanes of a plurality of lanes are enabled and which are disabled for the operation.
Kai Troester, Scott Thomas Bingham, John M. King, Michael Estlick, Erik Swanson, Robert Weidner
Filed: 27 Sep 19
Utility
Techniques to create power connections from floating nets in standard cells
19 Dec 23
A system and method for creating layout for standard cells are described.
Partha Pratim Ghosh, Pratap Kumar Das, Prasanth M
Filed: 4 Oct 21