10908 patents
Page 41 of 546
Utility
Microelectronic assemblies having conductive structures with different thicknesses
22 Aug 23
Microelectronic assemblies, and related devices and methods, are disclosed herein.
Brandon C. Marin, Andrew James Brown, Rahul Jain, Dilan Seneviratne, Praneeth Kumar Akkinepally, Frank Truong
Filed: 6 Feb 19
Utility
Selective ground flood around reduced land pad on package base layer to enable high speed land grid array (LGA) socket
22 Aug 23
Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate.
Zhichao Zhang, Gregorio R. Murtagian, Kuang C. Liu, Kemal Aygun
Filed: 22 Feb 22
Utility
Uniform layouts for SRAM and register file bit cells
22 Aug 23
Uniform layouts for SRAM and register file bit cells are described.
Zheng Guo, Clifford L. Ong, Eric A. Karl, Mark T. Bohr
Filed: 22 Jun 17
Utility
Harvesting energy in an integrated circuit using the seebeck effect
22 Aug 23
An apparatus includes a first semiconductor fin and a second semiconductor fin that is parallel to the first semiconductor fin.
Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
Filed: 1 Apr 16
Utility
Magnetic memory devices and methods of fabrication
22 Aug 23
A memory device includes a first electrode, a conductive layer including iridium above the first electrode and a magnetic junction directly on the conductive layer.
Daniel Ouellette, Christopher Wiegand, Justin Brockman, Tofizur Rahman, Oleg Golonzka, Angeline Smith, Andrew Smith, James Pellegren, Michael Robinson, Huiying Liu
Filed: 27 Mar 19
Utility
Method and system of automatic speech recognition with highly efficient decoding
22 Aug 23
A system, article, and method of automatic speech recognition with highly efficient decoding is accomplished by frequent beam width adjustment.
Piotr Rozen, Joachim Hofer
Filed: 9 Aug 21
Utility
Active package cooling structures using molded substrate packaging technology
22 Aug 23
Package assemblies with a molded substrate comprising fluid conduits.
Omkar Karhade, Mitul Modi, Edvin Cetegen, Aastha Uppal
Filed: 27 Feb 19
Utility
Metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements
22 Aug 23
Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area.
Yu-Lin Chao, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya
Filed: 25 Oct 21
Utility
Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers
22 Aug 23
A foundation layer and methods of forming a conductive via are described.
Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Robert A. May, Kristof Darmawikarta, Javier Soto Gonzalez, Kwangmo Lim
Filed: 13 Jul 21
Utility
Heterogeneous nested interposer package for IC chips
22 Aug 23
Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages.
Debendra Mallik, Ravindranath Mahajan, Robert Sankman, Shawna Liff, Srinivas Pietambaram, Bharat Penmecha
Filed: 11 Jun 19
Utility
Coaxial magnetic inductors with pre-fabricated ferrite cores
22 Aug 23
Embodiments include an inductor, a method to form the inductor, and a semiconductor package.
Kaladhar Radhakrishnan, Krishna Bharath, Clive Hendricks
Filed: 8 Oct 19
Utility
Methods to embed magnetic material as first layer on coreless substrates and corresponding structures
22 Aug 23
Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material.
Cheng Xu, Kyu-Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park, Sai Vadlamani, Seo Young Kim
Filed: 28 Jun 22
Utility
Aligned core balls for interconnect joint stability
22 Aug 23
Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned.
Jimin Yao, Shawna Liff, Xin Yan, Numair Ahmed
Filed: 25 Mar 19
Utility
Microelectronic package with solder array thermal interface material (SA-TIM)
22 Aug 23
Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate.
Debendra Mallik, Sergio Antonio Chan Arguedas, Jimin Yao, Chandra Mohan Jha
Filed: 25 Jun 19
Utility
Microelectronic structures including bridges
22 Aug 23
Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods.
Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Anurag Tripathi, Takeshi Nakazawa, Steve Cho
Filed: 10 May 22
Utility
Fan out packaging pop mechanical attach method
22 Aug 23
Embodiments include semiconductor packages and a method of forming the semiconductor packages.
David O'Sullivan, Georg Seidemann, Richard Patten, Bernd Waidhas
Filed: 4 Apr 18
Utility
Thin film tunnel field effect transistors having relatively increased width
22 Aug 23
Thin film tunnel field effect transistors having relatively increased width are described.
Prashant Majhi, Brian S. Doyle, Ravi Pillarisetty, Abhishek A. Sharma, Elijah V. Karpov
Filed: 14 Apr 22
Utility
Integrated circuit structures with source or drain dopant diffusion blocking layers
22 Aug 23
Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers.
Cory Bomberger, Anand Murthy, Anupama Bowonder, Aaron Budrevich, Tahir Ghani
Filed: 3 Jan 19
Utility
Field effect transistors having ferroelectric or antiferroelectric gate dielectric structure
22 Aug 23
Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described.
Seiyon Kim, Uygar E. Avci, Joshua M. Howard, Ian A. Young, Daniel H. Morris
Filed: 28 Sep 17
Utility
Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium NMOS transistors
22 Aug 23
Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication.
Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Cory C. Bomberger, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey
Filed: 8 Oct 21