467 patents
Utility
Transmitter architecture for high speed memory interfaces
16 Jan 24
Embodiments included herein are directed towards a transmitter circuit.
Vinod Kumar
Filed: 24 Jun 22
Utility
Dynamically updated delay line
16 Jan 24
The present disclosure relates to dynamically updating a delay line code.
Hajee Mohammed Shuaeb Fazeel, Jitendra Kumar Yadav, Thomas Evan Wilson
Filed: 26 Apr 22
Utility
Multi-stage equalizer for inter-symbol interference cancellation
16 Jan 24
An equalizer includes a first feed-forward stage that provides a measure of low-frequency ISI and a second feed-forward stage that includes a cascade of stages each making an ISI estimate.
Prashant Choudhary, Nanyang Wang
Filed: 1 Nov 22
Utility
Method and system for optimizing a verification test regression
9 Jan 24
A method for optimizing a verification regression includes obtaining data, by a processor, of previously executed runs of at least one verification regression session; extracting from the data, by the processor, values of one or a plurality of control knobs and values of one or a plurality verification metrics that were recorded during the execution for each of the previously executed runs of said at least one verification regression; finding, by the processor, correlation between said one or a plurality of the control knobs and each said one or a plurality of verification metrics, and generating a set of one or a plurality of control conditions based on the found correlation; and applying, by the processor, the generated set of one or a plurality of control conditions on the verification environment or on the DUT, or on both, to obtain a new verification regression session.
Yael Kinderman, Yosinori Watanabe, Michele Petracca, Ido Avraham
Filed: 10 Dec 19
Utility
Driver resizing using a transition-based pin capacitance increase margin
9 Jan 24
Aspects of the present disclosure address systems and methods for driver resizing using a transition-based capacitance increase margin.
Jhih-Rong Gao, Yi-Xiao Ding, Zhuo Li
Filed: 31 Mar 21
Utility
Context-aware circuit design layout construct
9 Jan 24
Various embodiments provide for context-aware circuit design layout construct, which may be part of electronic design automation (EDA).
Joshua David Tygert, Jonathan R. Fales, Rwik Sengupta, Timothy H. Pylant
Filed: 2 Dec 21
Utility
Systems and methods for distributed and parallelized emulation processor configuration
9 Jan 24
Implementations may include a method of accelerated modification of an emulation processor system, by loading, by a first emulation processor, a first portion of processor instructions into one or more registers of the first emulation processor, in response to a selection of a first programming mode associated with the first emulation processor, and loading, by a second emulation processor operatively coupled with the first emulation processor, a second portion of the processor instructions into one or more registers of the second emulation processor, in response to a selection of a first programming mode associated with the second emulation processor.
Ngai Ngai William Hung, Amiya Ranjan Satapathy
Filed: 14 Jan 22
Utility
Method and System to Facilitate Review of Schematics for an Electronic Design
4 Jan 24
Disclosed is a method and system for visualizing schematic changes for an electronic design, where multiple schematic view interfaces are provided such that a first schematic interface displays an older schematic version and a second schematic interface displays a newer schematic version.
Arnold Ginetti
Filed: 30 Jun 22
Utility
Molecular Structure Editor with Version Control and Simultaneous Editing Operations
4 Jan 24
Computer-based methods that permit two or more users to perform simultaneous edits on a digitally encoded molecular structure.
Jharrod LAFON
Filed: 27 Mar 23
Utility
System and method for routing in an electronic design
2 Jan 24
Embodiments include herein are directed towards a method for electronic circuit design.
Pratul Kumar Singh
Filed: 16 Sep 21
Utility
Quantized softmax layer for neural networks
2 Jan 24
Quantized softmax layers in neural networks are described.
Ming Kai Hsu
Filed: 17 Jun 19
Utility
Quantizing trained neural networks with removal of normalization
2 Jan 24
Various embodiments provide for quantizing a trained neural network with removal of normalization with respect to at least one layer of the quantized neural network, such as a quantized multiple fan-in layer (e.g., element-wise add or sum layer).
Ming Kai Hsu
Filed: 26 Dec 19
Utility
Method, product, and system for dynamic design switching for high performance mixed signal simulation
19 Dec 23
An approach is disclosed herein for dynamic design switching for high performance mixed signal simulation.
Qingyu Lin, Patrick O'Halloran, Xiao Wang
Filed: 30 Nov 21
Utility
Model-based simulation result predictor for circuit design
12 Dec 23
Various embodiments provide for predicting a simulation result for a circuit design using a machine learning model, which can be used as part of a process of an electronic design automation (EDA) system that measures a circuit design (e.g., timing, power, voltage, current, etc.).
Saleha Khatun, David Varghese, Roland Ruehl
Filed: 15 Oct 21
Utility
Serializing and deserializing stage testing
28 Nov 23
A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value.
Angus William McLaren, Robert A. Heaton, Aaron Ali, Frederick A. Ware
Filed: 14 Jun 22
Utility
System and method for monitoring compliance patterns
28 Nov 23
Embodiments include herein are directed towards a system and method for monitoring compliance patterns.
Kunal Amar Chhabriya, Roque Alejandro Arcudia Hernandez, Xin Mu
Filed: 23 Feb 22
Utility
System, method, and computer program product for predicting pin placement in an electronic design
28 Nov 23
The present disclosure relates to a computer-implemented method for automatically determining pin placement associated with an electronic design.
Sai Bhushan, Chirag Ahuja
Filed: 31 Aug 20
Utility
High-bandwidth signal driver/receiver
28 Nov 23
A tuned single-coil inductor is implemented between a signal driver output and external contact of an ESD-protected integrated circuit (IC) die and more specifically between the parasitic capacitances of the signal driver and the contact-coupled ESD (electrostatic discharge) element to form a Pi (π) filter that enhances signaling bandwidth at the target signaling rate of the IC die.
Phalguni Bala, Manjunath Karikatti, Navin Kumar Mishra
Filed: 28 Jul 20
Utility
Low power current mode logic
28 Nov 23
High-speed signal propagation circuits are biased by a temperature-compensating signal-swing calibrator to yield a target output signal amplitude across process, voltage and temperature corners, avoiding the power-consumptive over-biasing conventionally employed to avoid under-amplitude conditions in slow-process, low-voltage and/or high temperature conditions.
Sambasiva Rao Udatha, Uma Suri Appa Rao Kandregula
Filed: 28 Jul 22
Utility
Methods and circuits for reducing clock jitter
28 Nov 23
A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry.
Marcus Van Ierssel, Prabhnoor Singh Kainth, Nanyan Wang
Filed: 13 Apr 22