157 patents
Page 3 of 8
Utility
Precise Data Tuning Method and Apparatus for Analog Neural Memory In an Artificial Neural Network
24 Nov 22
Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 27 Jul 22
Utility
Non-volatile Memory Cell Array Formed In a P-well In a Deep N-well In a P-substrate
24 Nov 22
Numerous embodiments are disclosed of a non-volatile memory cell array formed in a p-well, which is formed in a deep n-well, which is formed in a p-substrate.
Hieu Van Tran, Nhan Do
Filed: 30 Aug 21
Utility
Precision Tuning of a Page or Word of Non-volatile Memory Cells In an Analog Neural Memory System
20 Oct 22
Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed.
Hieu Van Tran, THUAN VU, STEPHEN TRINH, STANLEY HONG, ANH LY, STEVEN LEMKE, VIPIN TIWARI, NHAN DO
Filed: 1 Jul 22
Utility
Precision Tuning of a Page or Word of Non-volatile Memory Cells In an Analog Neural Memory System
20 Oct 22
Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed.
Hieu Van Tran, THUAN VU, STEPHEN TRINH, STANLEY HONG, ANH LY, STEVEN LEMKE, VIPIN TIWARI, NHAN DO
Filed: 4 Jul 22
Utility
Ultra-precise Tuning of Neural Memory Cells
20 Oct 22
Examples for ultra-precise tuning of a selected memory cell are disclosed.
Steven Lemke, Hieu Van Tran, Yuri Tkachev, Louisa Schneider, Henry A. Om'mani, Thuan Vu, Nhan Do, Vipin Tiwari
Filed: 27 Jun 22
Utility
Testing of Analog Neural Memory Cells In an Artificial Neural Network
6 Oct 22
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks.
Hieu Van TRAN, Thuan VU, Stephen TRINH, Stanley HONG, Anh LY, Steven LEMKE, Nha NGUYEN, Vipin TIWARI, Nhan DO
Filed: 15 Jun 22
Utility
Virtual Ground Non-volatile Memory Array
6 Oct 22
A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates.
Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
Filed: 21 Jun 22
Utility
Split-gate Flash Memory Cell with Improved Control Gate Capacitive Coupling, and Method of Making Same
15 Sep 22
A method of forming a memory device that includes forming a first insulation layer, a first conductive layer, and a second insulation layer on a semiconductor substrate, forming a trench in the second insulation layer to expose the upper surface of the first conductive layer, performing an oxidation process and a sloped etch process to reshape the upper surface to a concave shape, forming a third insulation layer on the reshaped upper surface, forming a conductive spacer on the third insulation layer, removing portions of the first conductive layer leaving a floating gate under the conductive spacer with the reshaped upper surface terminating at a side surface at a sharp edge, and forming a word line gate laterally adjacent to and insulated from the floating gate.
Leo Xing, CHUNMING WANG, XIAN LIU, NHAN DO, GUO XIANG SONG
Filed: 14 Jun 21
Utility
Method of Forming a Semiconductor Device with Memory Cells, High Voltage Devices and Logic Devices on a Substrate
1 Sep 22
A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the three areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in all three areas, forming a protective layer in the first and second areas and then removing the third conductive layer from the third area, then forming blocks of dummy conductive material in the third area, then etching in the first and second areas to form select and HV gates, and then replacing the blocks of dummy conductive material with blocks of metal material.
Guo Xiang Song, Chunming Wang, Leo Xing, Xian Liu, Nhan Do
Filed: 4 Jun 21
Utility
Programming Analog Neural Memory Cells In Deep Learning Artificial Neural Network
11 Aug 22
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 2 May 22
Utility
Method Of Forming A Device With Split Gate Non-volatile Memory Cells, HV Devices Having Planar Channel Regions And FINFET Logic Devices
21 Jul 22
A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.
Serguei Jourba, CATHERINE DECOBERT, FENG ZHOU, JINHO KIM, XIAN LIU, NHAN DO
Filed: 8 Apr 22
Utility
Architectures for Storing and Retrieving System Data In a Non-volatile Memory System
30 Jun 22
Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system.
Xian Liu, Chunming Wang, Nhan Do, Hieu Van Tran
Filed: 11 Mar 21
Utility
Word Line and Control Gate Line Tandem Decoder for Analog Neural Memory In Deep Learning Artificial Neural Network
2 Jun 22
Various embodiments of tandem row decoders are disclosed.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
Filed: 15 Feb 22
Utility
Deep Learning Neural Network Classifier Using Non-volatile Memory Array
12 May 22
An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses.
FARNOOD MERRIKH BAYAT, XINJIE GUO, DMITRI STRUKOV, NHAN DO, HIEU VAN TRAN, VIPIN TIWARI, MARK REITEN
Filed: 21 Jan 22
Utility
Split Gate Non-volatile Memory Cells, HV and Logic Devices with Finfet Structures, and Method of Making Same
5 May 22
A method of forming memory cells, high voltage devices and logic devices on fins of a semiconductor substrate's upper surface, and the resulting memory device formed thereby.
Guo Xiang Song, CHUNMING WANG, LEO XING, XIAN LIU, NHAN DO
Filed: 19 Jan 21
Utility
Wear Leveling In Eeprom Emulator Formed of Flash Memory Cells
28 Apr 22
The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM.
Guangming Lin, Xiaozhou Qian, Xiao Yan Pl, Vipin Tiwari, Zhenlin Ding
Filed: 7 Jan 22
Utility
Split-gate, 2-BIT Non-volatile Memory Cell with Erase Gate Disposed Over Word Line Gate, and Method of Making Same
31 Mar 22
A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions.
CHUNMING WANG, XIAN LIU, GUO XIANG SONG, LEO XING, NHAN DO
Filed: 19 Jan 21
Utility
Split-gate Non-volatile Memory Cells with Erase Gates Disposed Over Word Line Gates, and Method of Making Same
31 Mar 22
A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.
Chunming Wang, Xian Liu, Guo Xiang Song, Leo Xing, Nhan Do
Filed: 2 Feb 21
Utility
Method of Forming a Device with Planar Split Gate Non-volatile Memory Cells, High Voltage Devices and Finfet Logic Devices
24 Mar 22
A method of forming memory cells, HV devices and logic devices on a substrate, including recessing the upper surface of the memory cell and HV device areas of the substrate, forming a polysilicon layer in the memory cell and HV device areas, forming first trenches through the first polysilicon layer and into the silicon substrate in the memory cell and HV device areas, filling the first trenches with insulation material, forming second trenches into the substrate in the logic device area to form upwardly extending fins, removing portions of the polysilicon layer in the memory cell area to form floating gates, forming erase and word line gates in the memory cell area, HV gates in the HV device area, and dummy gates in the logic device area from a second polysilicon layer, and replacing the dummy gates with metal gates that wrap around the fins.
Chunming Wang, Guo Xiang Song, Leo Xing, Jack Sun, Xian Liu, Nhan Do
Filed: 19 Jan 21
Utility
Concurrent Write and Verify Operations In an Analog Neural Memory
3 Mar 22
Numerous embodiments of analog neural memory systems that enable concurrent write and verify operations are disclosed.
Hieu Van Tran
Filed: 2 Mar 21