157 patents
Page 5 of 8
Utility
Ultra-precise Tuning of Analog Neural Memory Cells In a Deep Learning Artificial Neural Network
26 Aug 21
Embodiments for ultra-precise tuning of a selected memory cell are disclosed.
Steven Lemke, Hieu Van Tran, Yuri Tkachev, Louisa Schneider, Henry A. Om'Mani, Thuan Vu, Nhan Do, Vipin Tiwari
Filed: 4 Aug 20
Utility
Wear Leveling In Eeprom Emulator Formed of Flash Memory Cells
26 Aug 21
The present invention relates to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM.
Guangming Lin, Xiaozhou Qian, Xiao Yan Pi, Vipin Tiwari, Zhenlin Ding
Filed: 28 Aug 20
Utility
Set-While-Verify Circuit And Reset-While Verify Circuit For Resistive Random Access Memory Cells
19 Aug 21
Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed.
HIEU VAN TRAN, ANH LY, THUAN VU, STANLEY HONG, FENG ZHOU, XIAN LIU, NHAN DO
Filed: 11 Mar 21
Utility
Programming Analog Neural Memory Cells In Deep Learning Artificial Neural Network
19 Aug 21
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 3 Mar 21
Utility
Flash Memory Cell and Associated High Voltage Row Decoder
5 Aug 21
The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells.
Hieu Van Tran, Anh Ly, Thuan Vu
Filed: 23 Apr 21
Utility
Verification of a Weight Stored In a Non-volatile Memory Cell In a Neural Network Following a Programming Operation
29 Jul 21
Numerous embodiments are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory.
FARNOOD MERRIKH BAYAT, XINJIE GUO, DMITRI STRUKOV, NHAN DO, HIEU VAN TRAN, VIPIN TIWARI, MARK REITEN
Filed: 16 Apr 21
Utility
Precise Data Tuning Method and Apparatus for Analog Neural Memory In an Artificial Neural Network
8 Jul 21
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 25 Mar 20
Utility
Circuitry to Compensate for Data Drift In Analog Neural Memory In an Artificial Neural Network
8 Jul 21
Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system.
Hieu Van Tran, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
Filed: 26 Mar 20
Utility
Precise Data Tuning Method and Apparatus for Analog Neural Memory In an Artificial Neural Network
8 Jul 21
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, STEVEN LEMKE, NHAN DO, MARK REITEN
Filed: 25 Feb 21
Utility
CorrectedProgramming Circuit and Method For Flash Memory Array
8 Jul 21
An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.
Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
Filed: 17 Sep 19
Utility
Method Of Forming A Device With Split Gate Non-volatile Memory Cells, HV Devices Having Planar Channel Regions And FINFET Logic Devices
24 Jun 21
A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.
Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
Filed: 20 Dec 19
Utility
Output Circuits for an Analog Neural Memory System for Deep Learning Neural Network
10 Jun 21
Numerous output circuits are disclosed for an analog neural memory system for a deep learning neural network.
Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
Filed: 22 Feb 21
Utility
Virtual Ground Non-volatile Memory Array
10 Jun 21
A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates.
Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
Filed: 18 Feb 21
Utility
Low Voltage Level Shifter For Integrated Circuit
3 Jun 21
An improved level shifter is disclosed.
Ryan Mei, XIAOZHOU QIAN, HIEU VAN TRAN, CLAIRE ZHU
Filed: 2 Apr 20
Utility
Precise Programming Method And Apparatus For Analog Neural Memory In An Artificial Neural Network
13 May 21
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 23 Jan 20
Utility
Verifying or Reading a Cell In an Analog Neural Memory In a Deep Learning Artificial Neural Network
13 May 21
Numerous embodiments of programming, verifying, and reading systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 17 Dec 20
Utility
Input and Digital Output Mechanisms for Analog Neural Memory In a Deep Learning Artificial Neural Network
22 Apr 21
Numerous embodiments for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Toan Le, Nghia Le, Hien Pham
Filed: 23 Dec 20
Utility
Input and Digital Output Mechanisms for Analog Neural Memory In a Deep Learning Artificial Neural Network
1 Apr 21
Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
Filed: 14 Dec 20
Utility
Precision Tuning for the Programming of Analog Neural Memory In a Deep Learning Artificial Neural Network
25 Mar 21
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 19 Sep 19
Utility
Temperature Compensation In an Analog Memory Array by Changing a Threshold Voltage of a Selected Memory Cell In the Array
25 Mar 21
Numerous embodiments are disclosed for providing temperature compensation in an analog memory array.
Hieu Van Tran, Steven Lemke, Nhan Do, Vipin Tiwari, Mark Reiten
Filed: 11 Nov 20