805 patents
Utility
Artificial Intelligence (Ai)/machine Learning (ML) Tensor Processor
18 Jan 24
A system for executing tensor operations including: a programmable tensor processor; and a memory coupled to the programmable tensor processor, wherein the programmable tensor processor includes: one or more load AGU circuits to generate a first sequence of addresses and read input tensor operands from the memory based on the first sequence of addresses; a datapath circuit to perform the tensor operations on the input tensor operands based on receiving one or more instructions to determine output tensor operands, the one or more instructions being based on a loop iteration count and loop body micro-code instructions defining a loop body of a tensor program stored in the memory, the loop body micro-code instructions being executed in the programmable tensor processor; and a store AGU circuit configured to generate a second sequence of addresses and write the output tensor operands to the memory based on the second sequence of addresses.
Johannes Boonstra
Filed: 24 May 23
Utility
Stochastic optical proximity corrections
16 Jan 24
A method of improving mask data used in fabrication of a semiconductor device includes, in part, setting a threshold value associated with a defect based on stochastic failure rate of the defect, performing a first optimal proximity correction (OPC) of the mask data using nominal values of mask pattern contours, identifying locations within the first OPC mask data where stochastically determined mask pattern contours may lead to the defect, placing check figures on the identified locations to enable measurement of distances between the stochastically determined mask pattern contours, and performing a second OPC of the first OPC mask data so as to cause the measured distances to be greater than the threshold value.
Zachary Levinson, Yunqiang Zhang
Filed: 24 Feb 21
Utility
Non-fighting level shifters
16 Jan 24
A level shifter circuit includes a first current mirror coupled between a power terminal and a ground terminal, a second current mirror coupled between the power terminal and the ground terminal, and a level shifter.
Peter Kwang Lee, Kapil Dev Dwivedi, John Edward Barth
Filed: 12 Nov 21
Utility
System and method for optimizing emulation throughput by selective application of a clock pattern
9 Jan 24
A system is disclosed that includes a memory, and a processor configured to perform operations stored in the memory.
Bojan Mihajlovic, Alexander Rabinovitch, Fei Chen
Filed: 14 May 20
Utility
Lightweight unified power format implementation for emulation and prototyping
9 Jan 24
A method for designing a circuit includes adding, to a circuit design, a power switch configured to produce only one output over an acknowledgement port.
Swarup Kumar Pattanayak, Prathamesh Chandrashekhar Joshi
Filed: 16 Dec 21
Utility
Efficient Look-up Table Based Functions for Artificial Intelligence (Ai) Accelerator
4 Jan 24
A method for approximating an activation function, the method including: receiving an input value of the activation function; determining that the input value is within a range, the range includes a set of non-uniform intervals; determining a selected interval from among the set of non-uniform intervals including the input value; retrieving, by a hardware accelerator, from a look-up table (LUT) associated with a type of the activation function, values of one or more quadratic interpolation parameters associated with the selected interval; performing a quadratic interpolation on the input value to approximate the input value using the values of the one or more quadratic interpolation parameters; and determining a first approximated output of the activation function based on a result of the quadratic interpolation performed on the input value.
Johannes Boonstra
Filed: 26 May 22
Utility
Machine learning delay estimation for emulation systems
2 Jan 24
A delay estimation system estimates a delay of a DUT for an emulation system.
Yanhua Yi, Yu Yang, Jiajun Fan, Vinod Kumar Nakkala, Vijay Sundaresan, Jianfeng Huang
Filed: 10 Dec 21
Utility
Skeleton representation of layouts for the development of lithographic masks
2 Jan 24
In certain embodiments, a method includes the following steps.
Thomas C. Cecil, David W. Thomas
Filed: 19 Feb 21
Utility
Deterministic data latency in serializer/deserializer-based design for test systems
2 Jan 24
Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT.
Abhijeet Samudra, Ajay Nagarandal, Anubhav Sinha, Luis M. Cruz, Milin Kaushik Raijada, Ramalingam Kolisetti, Naresh Thakur, Saransh Nagaich, Jatin Verma
Filed: 17 Jun 22
Utility
Segregating defects based on computer-aided design (CAD) identifiers associated with the defects
2 Jan 24
For each defect in a set of defects, the defect may be associated with a defect attribute constructed from a set of computer-aided design (CAD) identifiers associated with polygons in an integrated circuit (IC) design that overlap with a defect area of the defect.
Ankush B. Oberai, Kiran U. Agashe
Filed: 29 Jun 21
Utility
Unwanted peak reduction in equalizer
2 Jan 24
An equalizer circuit includes: a main stage circuit including: a main stage differential pair; and a main stage degeneration resistance; a replica stage circuit including: a replica stage differential pair matching the main stage differential pair; and a replica stage degeneration resistance matching the main stage degeneration resistance and disconnected from the replica stage differential pair; equalizer inputs connected to: gate electrodes of the main stage differential pair; and gate electrodes of the replica stage differential pair; and equalizer outputs connected to: a main stage positive output and a main stage negative output connected to drain electrodes of the main stage differential pair; and a replica stage positive output and a replica stage negative output connected to drain electrodes of the replica stage differential pair, the replica stage positive output connected to the main stage negative output and the replica stage negative output connected to the main stage positive output.
Jayesh Wadekar, Jairaj Naik K R, Atul Kabra
Filed: 21 Jul 22
Utility
D-type wholly dissimilar high-speed static set-reset flip flop
2 Jan 24
A circuit is provided.
Pradip Jadhav, Michael McManus
Filed: 3 Jun 22
Utility
Phase Mixer Non-linearity Measurement Within Clock and Data Recovery Circuitry
28 Dec 23
A system and method that measures the code non-linearity of a phase mixer (PMIX) during active operation of a clock and data recovery (CDR) circuitry.
Ayal S. SHOVAL, John T. STONICK, Michael W. LYNCH, Dino Anthony TOFFOLON
Filed: 28 Jun 22
Utility
Phase Mixer Non-linearity Compensation Within Clock and Data Recovery Circuitry
28 Dec 23
A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation.
Ayal S. SHOVAL, Tom THOMAS, Jin CHEN, John T. STONICK, Michael W. LYNCH, Dino Anthony TOFFOLON
Filed: 28 Jun 22
Utility
Synchronizing Distributed Simulations of a Circuit Design
21 Dec 23
A system and method for using a distributed simulation system includes simulating a first portion of the circuit design within a first simulation environment by a first client device to generate first simulation data.
Parijat BISWAS, Sitikant SAHU, Tilak Chand Vinay Kumar MEKA, Shivani JAIN
Filed: 21 Jun 22
Utility
Field-net for Placement Evaluation
21 Dec 23
The present disclosure describes a system and method for determining a function for a quality of results (QoR) for a circuit design.
Xiang GAO, Yi-Min JIANG, Manish SHARMA
Filed: 20 Jun 23
Utility
Integrated circuit design using multi-bit combinational cells
19 Dec 23
Embodiments herein describe a techniques for identifying a first combinational cell 210 in a design for an integrated circuit, identifying a plurality of candidate combinational cells 205 to combine with the first combinational cell using a first criterion.
Mayank Jain, Deepak Dattatraya Sherlekar, Mohammad Ziaullah Khan, Guilherme Augusto Flach, Linuo Xue, Jeff Ku, Jovanka Ciric Vujkovic
Filed: 4 Aug 21
Utility
Interference reducing passive transmission line receiver
19 Dec 23
The present disclosure relates to improved electronic structures for propagating logic states between superconducting digital logic gates using a three-junction interferometer in a receiver circuit to reduce reflecting signals that otherwise result in distortions in the signals being transmitted between the gates.
Stephen Whiteley
Filed: 22 Feb 21
Utility
Multi-cycle power analysis of integrated circuit designs
12 Dec 23
A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles; determining, by a processor, inferred logic vectors including inferred logic values corresponding to signals output by cells of the IC design based on propagating the recorded logic values of the recorded logic vectors through the cells; and computing per-cycle power characteristics of the IC design based on the recorded logic vectors and the inferred logic vectors.
George Guangqiu Chen, Solaiman Rahim
Filed: 9 Mar 22
Utility
Automated determinaton of failure mode distribution
12 Dec 23
A method includes tracing from an observation point in a circuit to an input of the circuit to produce a cone of influence that includes a plurality of components of the circuit.
Fadi Maamari, Shivakumar Shankar Chonnad, Abhishek Chauhan, Jamileh Davoudi
Filed: 22 Sep 21