1391 patents
Page 2 of 70
Utility
Batch transfer of commands and data in a secure computer system
2 Jan 24
A computing system includes a host device and a root of trust (RoT) device for performing batch encryption and decryption operations facilitated by a direct memory access (DMA) engine.
Ashish Raj, Joel Wittenauer, Winthrop John Wu, Qinglai Xiao, Samatha Gummalla, Bryan Jason Wang
Filed: 9 Dec 22
Utility
Stacked semiconductor device
2 Jan 24
A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies.
Frederick A. Ware
Filed: 22 Oct 21
Utility
Memory component for deployment in a dynamic stripe width memory system
2 Jan 24
In a memory component programmed to operate in a first operating mode and having a page buffer and a fixed-width data interface, N bits of a command/address value are decoded to access one of 2N columns of data within the page-buffer, with that column of data output via the fixed-width data interface over a first burst interval.
Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
Filed: 31 Jan 22
Utility
Packaged Integrated Device
28 Dec 23
Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals.
Shahram NIKOUKARY, Jonghyun CHO, Nitin JUNEJA, Ming LI
Filed: 5 Jul 23
Utility
Tag Processing for External Caches
28 Dec 23
A device includes a cache memory and a memory controller coupled to the cache memory.
Michael Miller, Dennis Doidge, Collins Williams
Filed: 26 Jun 23
Utility
Flash Memory Device Having a Calibration Mode
28 Dec 23
A method of operation of a flash integrated circuit (IC) memory device is described.
Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
Filed: 29 Jun 23
Utility
Memory controllers, systems, and methods supporting multiple request modes
28 Dec 23
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports.
Richard E. Perego, Frederick A. Ware
Filed: 23 Jun 23
Utility
Drift Detection In Timing Signal Forwarded from Memory Controller to Memory Device
21 Dec 23
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal.
Jun Kim, Pak Shing Chau, Wayne S. Richardson
Filed: 7 Jun 23
Utility
Method and Apparatus for Calibrating Write Timing In a Memory System
21 Dec 23
A system that calibrates timing relationships between signals involved in performing write operations is described.
Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
Filed: 14 Jun 23
Utility
Flash Memory Device with Photon Assisted Programming
21 Dec 23
A flash memory cell of a flash memory device is illuminated with light during programming and/or erasing.
Mark D. KELLAM
Filed: 5 Oct 21
Utility
High-throughput Low-latency Hybrid Memory Module
21 Dec 23
Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability.
Aws Shallal, Micheal Miller, Stephen Horn
Filed: 22 Jun 23
Utility
Protocol Including Timing Calibration Between Memory Request and Data Transfer
21 Dec 23
The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller.
Frederick A. Ware, Holden Jessup
Filed: 24 Apr 23
Utility
Memory System Topologies Including A Memory Die Stack
21 Dec 23
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices.
Ian Shaeffer, Ely Tsem, Craig Hampel
Filed: 23 Jun 23
Utility
Configurable, Power Supply Voltage Referenced Single-ended Signaling with Esd Protection
21 Dec 23
A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage.
John W. POULTON, Frederick A. WARE, Carl W. WERNER
Filed: 10 May 23
Utility
Determining Integrity-driven Error Types In Memory Buffer Devices
14 Dec 23
Technologies for detecting an error using a message authentication code (MAC) associated with cache line data and differentiating the error as having been caused by an attack on memory or a MAC verification failure caused by an ECC escape.
Evan Lawrence Erickson, Helena Handschuh, Michael Alexander Hamburg, Mark Evan Marson, Michael Raymond Miller
Filed: 26 May 23
Utility
Switch-based free memory tracking in data center environments
12 Dec 23
Computing devices, methods, and systems for switch-based free memory tracking in data center environments are disclosed.
Steven C. Woo, Christopher Haywood, Evan Lawrence Erickson
Filed: 20 Jan 22
Utility
Memory controller for strobe-based memory systems
12 Dec 23
An integrated circuit (IC) memory controller is disclosed.
Jade M. Kizer, Sivakumar Doraiswamy, Benedict Lau
Filed: 15 Sep 22
Utility
System application of DRAM component with cache mode
12 Dec 23
Disclosed is a memory system that has a memory controller and may have a memory component.
Frederick Ware, Thomas Vogelsang, Michael Raymond Miller, Collins Williams
Filed: 16 Mar 20
Utility
Memory system with multiple open rows per bank
12 Dec 23
A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently.
Thomas Vogelsang, John Eric Linstadt, Liji Gopalakrishnan
Filed: 30 Jul 21
Utility
Integrated circuit with configurable on-die termination
12 Dec 23
Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads.
Huy Nguyen
Filed: 20 Apr 21