1391 patents
Page 3 of 70
Utility
Memory Bandwidth Aggregation Using Simultaneous Access of Stacked Semiconductor Memory Die
7 Dec 23
A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die.
Yohan Frans
Filed: 10 May 23
Utility
Row Hammer Mitigation
7 Dec 23
A 3D DRAM architecture may have one or more layers of cells where the access transistors of the memory cell array are fabricated among the metal layers rather than in the semiconductor (e.g., silicon) substrate.
Thomas VOGELSANG, Torsten PARTSCH
Filed: 6 Jun 23
Utility
Encryption of Error Correction Data Using Symbol-level Ciphers
7 Dec 23
Aspects and implementations include systems and techniques for encryption and decryption of error-corrected codewords for combined protection against corruption of data and adversarial attacks, including obtaining a block of data that has a first plurality of symbols, generating, based on the first plurality of symbols, a second plurality of symbols, wherein the second plurality of symbols includes one or more error correction symbols for the first plurality of symbols, encrypting the second plurality of symbols using a set of symbol-level ciphers (SLCs) to obtain an encrypted plurality of symbols, and using the encrypted plurality of symbols in a computer operation.
Michael Alexander Hamburg
Filed: 1 Jun 23
Utility
Techniques for Storing Data and Tags In Different Memory Arrays
7 Dec 23
A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag.
Frederick A. Ware
Filed: 14 Jun 23
Utility
Memory system with cached memory module operations
5 Dec 23
Memory controllers, devices, modules, systems and associated methods are disclosed.
Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
Filed: 11 Dec 21
Utility
Error coalescing
5 Dec 23
A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol.
John Eric Linstadt
Filed: 29 Nov 22
Utility
Live Offset Cancellation of the Decision Feedback Equalization Data Slicers
30 Nov 23
A receiver utilizes loop-unrolled decision feedback equalization (DFE).
Mohammad Sadegh JALALI, Marcus VAN IERSSEL
Filed: 27 Apr 23
Utility
Periodic Calibration For Communication Channels By Drift Tracking
30 Nov 23
A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift.
Craig E. Hampel, Frederick A. Ware, Richard E. Perego
Filed: 23 Apr 23
Utility
DRAM interface mode with interruptible internal transfer operation
28 Nov 23
Memory controllers, devices, modules, systems and associated methods are disclosed.
Liji Gopalakrishnan, Frederick A. Ware, Brent S. Haukness
Filed: 4 Jan 22
Utility
Flash memory device having a calibration mode
28 Nov 23
A method of operation of a flash integrated circuit (IC) memory device is described.
Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
Filed: 15 Dec 22
Utility
Asynchronous arbitration across clock domains for register writes in an integrated circuit chip
28 Nov 23
A buffer chip includes a first interface to receive in-band register access commands from a host and a second interface to receive side-band register access commands from the host.
Srinivas Satish Babu Bamdhamravuri
Filed: 21 Oct 21
Utility
Memory controller with staggered request signal output
28 Nov 23
A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller.
Ian P. Shaeffer, Bret Stott, Benedict C. Lau
Filed: 25 Mar 22
Utility
Multiplicative Masking for Cryptographic Operations
23 Nov 23
A value corresponding to an input for a cryptographic operation may be received.
Michael Tunstall, Francois Durvaux
Filed: 5 Apr 23
Utility
a Far Memory Allocator for Data Center Stranded Memory
23 Nov 23
An integrated circuit device includes a first memory to support address translation between local addresses and fabric addresses and a processing circuit, operatively coupled to the first memory.
Evan Lawrence Erickson, Christopher Haywood
Filed: 11 Oct 21
Utility
Variable Width Memory Module Supporting Enhanced Error Detection and Correction
23 Nov 23
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems.
Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
Filed: 30 May 23
Utility
Dram Retention Test Method for Dynamic Error Correction
23 Nov 23
A method of operation in an integrated circuit (IC) memory device is disclosed.
Ely Tsern, Frederick A Ware, Suresh Rajan, Thomas Vogelsang
Filed: 24 Apr 23
Utility
Memory controller for micro-threaded memory operations
23 Nov 23
A micro-threaded memory device.
Frederick A. Ware, Craig E. Hampel, Wayne S. Richardson, Chad A. Bellows, Lawrence Lai
Filed: 23 Jun 23
Utility
Circuit and Method to Set Delay Between Two Periodic Signals with Unknown Phase Relationship
23 Nov 23
A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other.
Robert WANG, Zhuobin LI, Navid YAGHINI, Hemesh YASOTHARAN, Clifford TING
Filed: 19 May 23
Utility
High capacity memory system using standard controller component
21 Nov 23
The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode).
Frederick A. Ware, Suresh Rajan, Scott C. Best
Filed: 30 Jan 23
Utility
System including hierarchical memory modules having different types of integrated circuit memory devices
21 Nov 23
Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path.
Craig Hampel, Mark Horowitz
Filed: 21 Aug 20