1391 patents
Page 5 of 70
Utility
Interface Clock Management
2 Nov 23
The timing of the synchronous interface is controlled by a clock signal driven by a controller.
Yuanlong WANG
Filed: 8 May 23
Utility
Floating body dram with reduced access energy
31 Oct 23
Memory devices, controllers and associated methods are disclosed.
Frederick A. Ware, John Eric Linstadt, Zhichao Lu, Kenneth Lee Wright
Filed: 7 Apr 22
Utility
Memory with deferred fractional row activation
31 Oct 23
Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption.
James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
Filed: 7 Feb 22
Utility
Error remapping
31 Oct 23
Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address.
Christopher Haywood
Filed: 18 Apr 22
Utility
Cascaded memory system
31 Oct 23
A cascaded memory system includes a memory module having a primary interface coupled to a memory controller via a first communication channel and a secondary interface coupled to a second memory module via a second communication channel.
Christopher Haywood, Frederick A. Ware
Filed: 28 Apr 20
Utility
Memory with variable access granularity
31 Oct 23
An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data.
Frederick A. Ware
Filed: 5 Feb 20
Utility
Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling
31 Oct 23
A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus.
Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
Filed: 24 Jun 22
Utility
Phase Interpolator with Sub-period Phase Correction
26 Oct 23
A phase interpolator circuit has a first stage that selects a pair of phase vectors from among M available sets of pairs and a second stage that interpolates between the selected pair to phase align a sample clock.
Divanshu Chaturvedi
Filed: 18 Apr 23
Utility
Methods and Circuits for Aggregating Processing Units and Dynamically Allocating Memory
26 Oct 23
An application-specific integrated circuit for an artificial neural network is integrated with a high-bandwidth memory.
Steven C. Woo, Thomas Vogelsang
Filed: 30 Aug 21
Utility
Memory controller for micro-threaded memory operations
24 Oct 23
A micro-threaded memory device.
Frederick A. Ware, Craig E. Hampel, Wayne S. Richardson, Chad A. Bellows, Lawrence Lai
Filed: 7 May 19
Utility
Anti-tamper shield based on strings of series resistors
24 Oct 23
A resistor mesh with distributed sensing points is provided in a security chip as an anti-tamper shield.
Scott C. Best
Filed: 21 Aug 20
Utility
Security chip with resistance to external monitoring attacks
24 Oct 23
A method for performing a security chip protocol comprises receiving, by processing hardware of a security chip, a message from a first device as part of performing the security chip protocol.
Paul C. Kocher, Pankaj Rohatgi, Joshua M. Jaffe
Filed: 21 Jul 21
Utility
Memory Error Detection
19 Oct 23
Systems and methods are provided for detecting and correcting address errors in a memory system.
Ian Shaeffer, Craig E. Hampel
Filed: 10 Jan 23
Utility
Heterogenous-latency Memory Optimization
19 Oct 23
Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages.
Evan Lawrence Erickson, Christopher Haywood, Mark D. Kellam
Filed: 25 Apr 23
Utility
Memory Controller with Skew Compensated Data Transmit Timing
19 Oct 23
An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line.
Frederick A. Ware
Filed: 25 Apr 23
Utility
Strobe acquisition and tracking
17 Oct 23
A memory controller includes an interface to receive a data strobe signal and corresponding read data.
Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
Filed: 12 Jul 21
Utility
Memory component with efficient write operations
17 Oct 23
A memory component includes a first memory bank.
Frederick A. Ware, John Eric Linstadt, Brent Steven Haukness, Kenneth L. Wright, Thomas Vogelsang
Filed: 14 Jul 21
Utility
Phase modulated data link for low-swing wireline applications
17 Oct 23
A communication system comprises a transmitter and a receiver that communicate differential phase modulated data over a wireline channel pair.
Masum Hossain, Richelle L. Smith, Carl W. Werner
Filed: 29 Jun 22
Utility
Managing privileges of different entities for an integrated circuit
17 Oct 23
A request associated with one or more privileges assigned to a first entity may be received.
Benjamin Che-Ming Jun, William Craig Rawlings, Ambuj Kumar, Mark Evan Marson
Filed: 29 Jul 22
Utility
System and method of interfacing co-processors and input/output devices via a main memory system
17 Oct 23
A system for interfacing with a co-processor or input/output device is disclosed.
Michael L. Takefman, Maher Amer, Riccardo Badalone
Filed: 29 Jun 22