Surfect 8-K Regulation FD Disclosure

Exhibit 99.1

 

Management Presentation July 2006

 

The information in this presentation includes “forward-looking statements” (as such term is defined in the United States Private Securities Litigation Reform Act of 1995). Since these statements are based on factors that involve risks and uncertainties, actual results may differ materially from those expressed or implied by such “forward-looking statements”.

 

Table of Contents Business Overview Market Opportunity Customer Opportunity Addendum

 

Business Overview

 

Most advanced back end bumping interconnect semiconductor process (according to Applied Materials, K&S, Novellus) Founded in 2002 in Albuquerque Funding $6.1MM in Series A from ITU Ventures (Institutional VC) World class management team Steve Anderson (Amkor SVP), CEO, part of senior management team that took Amkor public, hired in July ‘05 to lead commercial introduction of the product Board includes Larry Wagner (VP KLA Tencor) Summary 2003 July 03 $375K of seed funding secured from ITU Ventures to complete semiconductor market research and determine business model 2004 $1MM in Series A from ITU to build electroless prototype and recruit CEO 2005 New CEO narrows target market and hires full team. $4.5MM funded to hire team and complete prototypes. 2006 Seeking funding for product roll-out

 

Business Summary Surfect has developed a new type of electroplating tool and deposition process that provides the electronics industry a way to fabricate high performance, low-cost interconnects Surfect’s deposition processes involves a revolutionary single-step process utilizing a novel “closed-cell” Provides immediate solutions facing the “back end” of the semiconductor manufacturing process Surfect is deep into significant sales ramp While many electroplating tools and processes exist, no product currently exists that provides the following benefits: High Speed Wafer Bumping Flexible Process Lead Free and Copper Capability Surfect is poised to pioneer the market for affordable flip chip packaging

 

Surfect’s Value Proposition Improved Manufacturability: Containerized chemistries – simplifies change-out Recipe driven process – eliminates timely setup, increases yield, provides repeatability and ease of use Innovative Multi-Alloy Deposition Capabilities: StrataPlate Process allows deposition of multi-alloy solders, including Pb-free combinatorial metals in single cell eliminates excess wafer handling and need for multiple deposition tools and steps Superior deposit uniformity and yield Critical Copper Interconnect: AggrePlate Process enables deposition of lower stress and higher performance copper interconnect using coated particles that targets reduced electro-migration issues and increases conductivity Lowest Cost of Ownership in the Industry: Individual cells cost approximately 1/4th that of currently available tools and require a fraction of the real estate. Single cell, small footprint, multiple processes and low handling result in significant cost savings

 

Management Steve Anderson, CEO: 20 year packaging industry veteran, from Amkor Technologies, TI and start-up companies. Significant role in taking Amkor public Marketing and technical development activities focused on electronics manufacturing, bringing new innovative interconnect technology to the semiconductor industry. Responsible for development, standardization of successful high volume single and multi-die semiconductor packages like MLF/QFN, TSSOP, exposed-pad CSP, system in package (SiP) as VP Product Management Amkor As President of Silicon Bandwidth, led the development of denser, high speed interconnect. Doug Welter, Chief Operating Officer: Mr. Welter is a 28 year Philips and Motorola veteran, and most recently VP and General Manager of Philip’s Standard IC business a WW division responsible for $300M business General Manager for the 1,000 person Philips Wafer Fab in Albuquerque, NM. General Manager Motorola for semiconductor equipment division handling automated test equipment, chip scale (CSP) packaging and CSP ball attach equipment with 70M$ in revenue David Hiner, VP Of Product Development: 15 year Amkor veteran, core developer of flip chip package technology Yixiang Xie, PhD, CTO: Dr. Xie has over 12 years experience in semiconductor development, 12 years prior material science experience, and hands-on C-4 and copper wafer bumping development and production ramp-up at Intel. Mark W. Eichhorn, Sales & Marketing:28 year veteran in the semiconductor capitol equipment sector with Kulicke & Soffa Industries. Extensive leadership responsibility serving back-end assembly market with expatriate positions in SE Asia/Japan. Experienced in all aspects of the customer operations arena to include sales, service, order processing, marketing alignments, executive level relations and business development. Solomon Basame, PhD: ENIG & Metrology expert Qiang Fu, PhD: Process Engineer & Nanoparticle focus Lee Moseley, BSEE: Control System & Software expert, Honeywell, Hughes, Sandia National Labs World Class Management and technical team

 

The Industry’s Problem Chips have continued to shrink in size, and the number of complex integrated circuits (“ICs”) per chip has dramatically increased. The dramatic increase in the number of I/Os on a chip combined with the rapid decrease in the size of chips renders a pitch, or distance that has created a challenge for interconnecting chips to the substrate. Legacy methods face significant challenges Wafer level packaging and 3-D designs are challenging industry Trend in manufacturing electronic systems is smaller, lighter, more reliable, higher performing and at the same time less expensive Mobile phones, digital cameras, computing, and consumer electronics are growth drivers. Interconnect fabrication is one of the key problems in the entire industry!

 

Flip Chip Technology now Standard Interconnect Gold and aluminum wire bonding processes: The method of making interconnections between a microchip and the outside world (package or substrate) as part of semiconductor device fabrication. Wire bonding presents obvious miniaturization and pitch density issues for next generation interconnect and packaging needs. Flip Chip Technology:A process of mounting a semiconductor device directly to the printed circuit board or substrate, after the creation of the interconnections (bumps of conductive solder material applied to each I/O on the wafer surface) on the wafer prior to wafer dicing. 200 & 300mm Wafers with bumps Copper Pillar multi-metal interconnect for uP, Analog, Automotive

 

Surfect’s Solution…….The Compact Plater A low-cost manufacturing tool that is able to deposit bumps on wafer at extremely high speeds and provides greater process flexibility. Customers have referred to it as the “Compact Plater Company” The following capabilities are unique to Surfect’s solution and will be discussed in greater detail. Innovative Multi-Alloy Deposition Superior deposit uniformity and yield Critical Copper Interconnect Capability Lowest Cost of Ownership in the Industry Copper/Nickel coated 300mm wafer for Asian-based Merchant Packager

 

Copper Enhanced Plating Development for 2006 Surfect proprietary AggrePlate™ process provides enhanced copper plating technology addressing electromigration issues with very fine features common below 65nm Micro-encapsulated materials that can be co-deposited within an electroplated layer “Aggreplated Deposition” Required for reduced lithography interconnect when pitch limitations force new solder solutions Nickel Core Aggreplate Solder Bump before/after reflow Copper and particle embedded plating are 2 major drivers for industry leaders

 

Market Opportunity

 

Flip Chip Outpacing Overall Market Flip Chip technology as the preferred high performance interconnect is spreading beyond traditional high performance Micro-processor, ASIC, and graphics applications into products such as Digital Signal Processor (DSP), RFID, and integrated 3D packages for mobile platforms. Growing from 7-8% of total interconnect marketshare today to 12.5% by 2010 or 23%/yr compounded growth rate The standard interconnection method for all microprocessors and graphics ICs providing high speed performance growing at 31%/yr Preferred technology for form factor driven applications such as wireless products growing at 24%/yr Electrodeposition technology approach for bumping provides the lowest defect level as well as tightest pitch capability available today Bumping demand driven by space efficient devices such as LCD driver ICs used in Flat Panel and Plasma TVs growing at 13%/yr Fast batch deposition method for RFIDs supporting thin metal layer requirements growing at 45%/yr

 

Flip Chip is the next wave of interconnect for packaging and Wafer level CSP devices such as RFID and wireless Prismark estimates current flip chip equipment at $200M with over 60 plating systems sold in 2005 according to Prismark Partners Larger market opportunity for $3B packaging flip chip market for copper and high performance interconnect as device technology migrates increasingly to wafer level and stacked die configurations Surfect’s process embedded in tool brings Programmable interconnect capability now only available in large $1.6B wire bond market Move to copper interconnect by Intel will drive opportunities for company’s low stress copper and enhanced conductivity process and materials DSP, Analog, Flash, DRAM, LCD display drivers driving growth Global Market Opportunity

 

Semiconductor Equipment & Packaging Trends Technology conversions have driven equipment leadership transitions Surfect’s interconnect solutions and management’s prior success creating Modified Leadframe market provides market leadership Hitachi Hi-Tech ASM International Ulvac 10 DaiNippon Canon Temescal 9 Canon DaiNippon JEOL 8 Novellus Systems Varian ASM International 7 Lam Research Silicon Valley Group MRC 6 KLA-Tencor Canon Varian 5 ASML Hitachi Hi-Tech Axcelis Technologies 4 Nikon Tokyo Electron Applied Materials 3 Tokyo Electron Applied Materials Perkin-Elmer 2 Applied Materials Nikon GCA 1 2000 1990 1980 Equipment Ranking Source: Prismark Source: Dataquest Bare Die (COB)Through Hole(TO & DIP)Surface Mount(SO, LCC, QFP, TAB)Modified Leadframe(QFN, MLF, MLP)Array Package(BGA, CSP)Flip Chip (DCA, WLP)202020152010200520001995WAVES OF ELECTRONICS PACKAGING1990198519800%10%20%30%40%50%60%70%80%90%100%Percent of Total ICsM13.088bp-waves

 

Customer Opportunity

 

Traction focused on largest available customers Representing over 22% of Worldwide TAM Leaders who will confirm technology for other firms representing over 70% TAM Leading companies for Processors, Graphics, Flash memory, and Analog products Engaged with all the major Taiwanese Merchant suppliers Surfect in evaluations and discussions supporting the largest companies using wafer level interconnect BUMPED WAFER PRODUCTION BY SUPPLIER(200mm Equivalent)B35.261jd-supplier2004TOTAL: 5.5M WAFERSAMD6%ASE5%Freescale3%TSMC3%SPIL2%IBM2%TI2%Delphi1%Other Japan(NEC, Toshiba, Fujitsu, Renesas)2%Others(small subcon, EM Micro, Matsushita)4%FCI1%Amkor/Unitive4%Intel21%Assorted Taiwanese/Chinese Gold Bumpers(Chipbond, Aptos, IST, Fupo, Megic, He Jian)22%Assorted Japanese Gold Bumpers(Casio, Sharp, NEC, Seiko Epson, Sanyo)22%

 

Addendum

 

Urgent Interconnect Process Solutions embedded in Tools The StrataPlate Process: Surfect has developed a process for creating controlled composition electronic solder alloys by sequential electrochemical deposition of the individual alloy constituent elements. The metals plating stack is deposited with a high degree of control. Enables use of individual metal baths addressing key IDM cost objective Creates alloys for high performance interconnect, lead-free and hybrid autos Thickness and sequence of constituent metal plating layers control composition Surfect’s StrataPlate Process is the only available single-cell multi-alloy deposition process available in the industryAu+Sn StrataPlate deposit prior to reflow Image of Au/Sn eutectic after one thermal cycle Uniform high density bumps formed

 

Advisors & Consultants Joel Camarda, Sr VP Operations Sipex Joel Camarda has 25 years experience in flip chip, engineering, operations and consulting management with Kulicke & Soffa, Silicon Storage Technology, IPAC, Cypress, NSC, Tessera, and other high tech companies. Andrew Murray, - Strategy & Finance: 5 year background in semiconductor startups, Founded Rocky Mountain Office for ITU Ventures, Formerly with Donaldson, Lufkin & Jenrette’s Investment Banking Group. CO & NM VCA member. Led investments in OnWafer, Pivotal Systems (Spin-out of Advanced Energy), Coatue (acq. By AMD), and Organic ID. Larry Wagner, VP of Business Development, KLA Tencor, Former President of FSI and Manager of wire bonding group at Kulicke & Soffa. Prior experience with Rohm & Haas. E&G Technology Partners, principals Pete Elenius and Tom Goodman. Mr. Elenius provides flip chip bumping expertise having worked at IBM, Flip Chip Technologies and K&S. Mr. Goodman provides product development expertise with previous positions at Sony, Motorola, Flip Chip Technologies. Neil Moskowitz, Prismark Partners, Neil is one of the premier flip chip industry researcher and former IBM interconnect specialist. He has worked with the company since 2002 and is engaged with most of the key companies in the electronics supply chain Jim Walker, VP Semiconductor Research, Gartner Dataquest Jim has 25 years experience in semiconductor manufacturing at NSC, Hana, and now Dataquest where he analyzes the equipment, packaging, and interconnect markets Pat Mentone Ph.D., Consultant Pat is a plating veteran starting at Buckbee-Mears both in US and Singapore as well as technical advisor to the Microelectronics and Computer Technology Corporation (MCC). He has development experience in plating technology for semiconductor, medical, and energy industries