3 patents
Utility
Methods for identifying integrated circuit failures caused by asynchronous clock-domain crossings in the presence of multiple modes
2 Mar 21
Methods and systems are described to identify potential failures caused by metastability arising from signal propagation between asynchronous clock domains in integrated circuits with multiple operating modes, each mode allowing selected clocks to propagate.
Vishnu Vimjam, Vikas Sachdeva, Prakash Narain, Paul Vyedin
Filed: 20 Feb 19
Utility
Methods for identifying integrated circuit failures caused by reset-domain interactions
2 Mar 21
Integrated circuit failures caused by metastability related to assertion of asynchronous resets frequently escape detection before fabrication, causing design respins and severe economic loss.
Oren Katzir, Sanjeev Mahajan, Prakash Narain, Vishnu Vimjam
Filed: 14 Feb 19
Utility
Methods and systems for efficient identification of glitch failures in integrated circuits
22 Jun 20
Methods and systems are described to efficiently identify the potential for failures in integrated circuits (ICs) caused by glitches.
Pranav Ashar, Fabrice Baray, Hari Mony, Nikhil Rahagude, Vikas Sachdeva
Filed: 7 Feb 19
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