53 patents
Utility
One by one selection of items of a set
2 Jan 24
An associative memory array includes a plurality of associative memory cells arranged in rows and columns where each first cell in a first row and in a first column has access to a content of a second cell in a second row in an adjacent column.
Moshe Lazer, Eli Ehrman
Filed: 2 Mar 21
Utility
Neural hashing for similarity search
19 Sep 23
A system for training a neural-network-based floating-point-to-binary feature vector encoder preserves the locality relationships between samples in an input space over to an output space.
Daphna Idelson
Filed: 24 Jun 21
Utility
Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
19 Sep 23
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function.
Lee-Lean Shu, Eli Ehrman
Filed: 2 Apr 21
Utility
Concurrent multi-bit subtraction in associative memory
12 Sep 23
A method for an associative memory device includes storing a plurality of pairs of multi-bit operands X and Y in rows of a memory array of the associative memory device, each pair in a different column of the memory array.
Moshe Lazer, Eyal Amiel
Filed: 23 Feb 22
Utility
In memory matrix multiplication and its usage in neural networks
22 Aug 23
A method for in memory computation of a neural network, the neural network having weights arranged in a matrix, includes previously storing the matrix in an associated memory device, receiving an input arranged in a vector and storing it in the memory device, and in-memory, computing an output of the network using the input and the weights.
Avidan Akerib, Pat Lasserre
Filed: 7 Mar 21
Utility
Efficient similarity search
9 May 23
A system for measuring similarity between a binary query vector and a plurality of binary candidate vectors includes a storage unit and a processor.
Samuel Lifsches
Filed: 8 Jul 20
Utility
In-memory full adder
14 Mar 23
A non-destructive memory array implements a full adder.
LeeLean Shu, Avidan Akerib
Filed: 13 Jan 20
Utility
In-memory efficient multistep search
6 Dec 22
A system for performing cascading search includes an associative memory array, a controller, a similarity search processor and an exact match processor.
Avidan Akerib
Filed: 6 May 20
Utility
Orthogonal data transposition system and method during data transfers to/from a processing array
9 Aug 22
A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory.
Bob Haig, Patrick Chuang, Chih Tseng, Mu-Hsiang Huang
Filed: 28 Oct 20
Utility
Write data processing methods associated with computational memory cells
22 Feb 22
A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.
Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 9 Oct 20
Utility
Storage array circuits and methods for computational memory cells
18 Jan 22
A storage array for computational memory cells formed as a memory/processing array provides storage of the data without using the more complicated computational memory cells for storage.
Lee-Lean Shu, Park Soon-Kyu, Paul M. Chiang
Filed: 4 Jun 18
Utility
Read data processing circuits and methods associated with computational memory cells
21 Dec 21
A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells.
Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 28 May 20
Utility
Results processing circuits and methods associated with computational memory cells
7 Dec 21
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
Bob Haig, Eli Ehrman, Dan Ilan, Patrick Chuang, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 13 Dec 19
Utility
Processing array device that performs one cycle full adder operation and bit line read/write logic features
7 Dec 21
Lee-Lean Shu, Bob Haig, Chao-Hung Chang
Filed: 6 Oct 20
Utility
Computational memory cell and processing array device using memory cells
19 Oct 21
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR.
Lee-Lean Shu, Chao-Hung Chang, Avidan Akerib
Filed: 8 Jun 20
Utility
Write data processing circuits and methods associated with computational memory cells
17 Aug 21
A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.
Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 26 Dec 19
Utility
Responder signal circuitry for memory arrays finding at least one cell with a predefined value
27 Jul 21
A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry.
Avidan Akerib, Eli Ehrman
Filed: 13 Dec 17
Utility
In memory matrix multiplication and its usage in neural networks
4 May 21
A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row R-matrix-row-j of the array, storing a vector in each associated column, where a bit j from the vector is stored in an R-vector-bit-j row of the array.
Avidan Akerib, Pat Lasserre
Filed: 23 Mar 17
Utility
Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
4 May 21
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function.
Lee-Lean Shu, Eli Ehrman
Filed: 19 Sep 17
Utility
One by one selection of items of a set
23 Mar 21
A method and a system for selecting items one by one from a set of items in an associative memory array includes determining a density of the set, if the density is sparse, repeatedly performing an extreme item select (EIS) method to select a next one of the elected items from the set and removing the next one from the set to create a next set, and if the density is not sparse, performing a next index select (NIS) method to create a linked list of the elected items and to repeatedly select a next elected item from the set.
Moshe Lazer, Eli Ehrman
Filed: 30 Aug 17