34 patents
Page 2 of 2
Utility
Computing device and neural network processor incorporating the same
28 Sep 21
The present application discloses a computing device and a neural network processor including the computing device.
Peng Wang, Chunyi Li
Filed: 18 May 20
Utility
Data conversion control apparatus, memory device and memory system
28 Sep 21
A data conversion control apparatus, comprising: at least one first interface each for coupling a first external interface, both of the first interface and the first external interface being in accordance with a predetermined physical interface standard, wherein data transmitted between the first interface and the first external interface is in accordance with a configurable application layer protocol; at least one second interface each for coupling a second external interface, wherein the second external interface is a memory interface in accordance with a predetermined memory interface standard, and the second interface is configurable to match the predetermined memory interface standard; and a data rebuild unit coupled between the at least one first interface and the at least one second interface, wherein the data rebuild unit is configured to rebuild data such that data can be transmitted in respective formats between the at least one first interface and the at least one second interface.
Gang Shan, Yi Li, Howard Chonghe Yang
Filed: 22 May 20
Utility
Phase locked loop-based power supply circuit and method, and chip
3 Aug 21
The present disclosure provides a phase locked loop-based power supply circuit and method, and a chip.
Gang Yan
Filed: 5 Nov 20
Utility
Communication device and skew correction method thereof
13 Apr 21
The present disclosure provides a communication device and a skew correction method thereof.
Jun Ma, Dan Wang, Zhongyuan Chang, Xin Liu
Filed: 10 Jun 20
Utility
Delay circuit, clock control circuit and control method
30 Mar 21
A delay circuit, a clock control circuit and a control method are disclosed.
Bo Qu, Jinfu Chen, Lixin Jiang
Filed: 30 Dec 19
Utility
Memory controller, method for performing access control to memory module
2 Mar 21
The application discloses a memory controller and a method for controlling an access to a memory module.
Gang Shan, Howard Chonghe Yang, Yi Li
Filed: 4 Jan 19
Utility
Memory controller and method for accessing memory modules and processing sub-modules
23 Feb 21
A memory controller and a method for accessing a memory module are provided.
Gang Shan, Howard Chonghe Yang, Yi Li
Filed: 4 Jan 19
Utility
Memory controller enabling dual-mode access to memory module
23 Feb 21
The application discloses a memory controller coupled to a memory module for controlling access to the memory module, wherein the memory module comprises one or more memory groups each having a plurality of memory blocks, and the memory controller comprising: a registering clock driver coupled to the memory module for providing to the memory module a data access command so as to control access to the memory module; one or more data buffers coupled to the registering clock driver, and each data buffer coupled to a memory group via a memory group data interface; wherein at least one of the memory group data interfaces comprises a plurality of data buses each coupled to one or more memory blocks of the memory group that the memory group data interface coupled to, such that the memory group can exchange data with the data buffer via the plurality of data buses under the control of the registering clock driver.
Qingjiang Ma, Gang Shan, Chunyi Li
Filed: 20 Dec 19
Utility
Fast phase frequency detector
4 Jan 21
A fast phase frequency includes two fast pulsed-latches, a NAND gate, and an adjustable delay circuit, where the fast pulsed-latches include a pulse generating circuit, a reset circuit, and an output latch circuit.
Pengzhan Zhang, Zhongyuan Chang, Yanhong Li
Filed: 24 Feb 20
Utility
Method for calibrating channel delay skew of automatic test equipment
14 Dec 20
The present invention relates to a method for calibrating a channel delay skew of automatic test equipment (ATE), the method comprising: providing multiple calibration reference devices, wherein the calibration reference devices have a second plurality of delay paths each having a predetermined path delay value and coupling a pair of pins of one of the calibration reference devices together, wherein each pin is coupled to at most one delay path; coupling each of the calibration reference devices with the ATE, respectively, wherein the test probe of each of the first plurality of test channels is coupled with a pin of one of the calibration reference devices; testing the calibration reference devices to obtain multiple delay measurements from one or more transmitting channels of the first plurality of test channels to one or more receiving channels of the first plurality of test channels using the ATE; and calculating based on the delay measurements.
Yong Wang, Dongming Lou, Weidong Fan, Ronghui Chen, Meng Mei
Filed: 10 Jul 19
Utility
Method and device for authenticating application that requests access to memory
2 Nov 20
The present application provides a method for authenticating an application that requests access to a memory, comprising: acquiring an authentication request provided by the application; acquiring a characteristic instruction provided by the application in response to the authentication request; acquiring an instruction pointer corresponding to the characteristic instruction; acquiring from the memory characteristic information of the application which is pre-stored in the memory based on the instruction pointer; and comparing the acquired characteristic information with authentication information corresponding to the application, so as to determine whether the authentication of the application is successful.
Gang Shan
Filed: 10 Jul 17
Utility
Time-to-digital converter and phase difference detection method
2 Nov 20
A time-to-digital converter and a phase difference detection method are disclosed.
Pengzhan Zhang, Yong Wang, Yanhong Li, Yaomin Wu, Zhongyuan Chang
Filed: 2 Mar 20
Utility
On-die termination control for memory systems
2 Mar 20
A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers, later than the target access CS signal, a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank; and wherein the target local controller is configured to generate, in response to receiving the target access CS signal, a target CA on-die termination (ODT) instruction switching on target CA ODT at its CA input at least for a period when the CA signal is being received from the memory controller.
Yibo Jiang, Gang Yan, Robert Xi Jin, Lizhi Jin, Leechung Yiu
Filed: 27 Jun 18
Utility
Method and device for protecting dynamic random access memory
18 Nov 19
A method for DRAM protection comprises allocating address spaces respectively for a first and second common region, a first and second secure region; detecting whether common data has an address within the address spaces for the first secure region; outputting a digital signal remapping an address of the common data to the address space for the second common region if yes; detecting whether secure data has an address within the address spaces for the first common region; outputting a digital signal indicating remapping an address of the secure data to the address space for the second secure region if yes.
Shuna Xu, Guobing Mo, Cheng-Tie Chen
Filed: 13 Mar 16