38 patents
Utility
High voltage semiconductor device comprising a combined junction terminal protection structure with a ferroelectric material and method of making the same
2 Jan 24
The present invention provides a high voltage semiconductor device comprising a combined junction terminal protection structure with a ferroelectric material and method of making the same, the device comprises: an active area formed with the high voltage semiconductor device; a combined junction terminal protection structure having a RESURF (Reduced Surface Field) structure, the RESURF structure comprising a first biasing field plate electrically connecting to the active area and a ferroelectric material layer positioned below the first biasing field plate and in contact with the first biasing field plate.
Min-Hwa Chi, Min Li, Richard Ru-Gin Chang
Filed: 18 Jun 21
Utility
ALD method with multi-chambers for sic or multi-elements epitaxial growth
5 Dec 23
The present invention relates to an ALD (Atomic layer deposition) apparatus and an ALD method.
Zhaosheng Meng, Zhuangzhuang Wu, Min-Hwa Chi
Filed: 28 Jan 22
Utility
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12 Oct 23
The present invention provides a power device with super junction structure (or referred to as super junction power device).
Min-Hwa CHI, Conghui LIU, Huan WANG, Longkang YANG
Filed: 13 Jun 23
Utility
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1 Aug 23
The present invention provides a power device with super junction structure (or referred to as super junction power device) and a method of making the same.
Min-Hwa Chi, Conghui Liu, Huan Wang, Longkang Yang
Filed: 11 Jun 21
Utility
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28 Feb 23
The present application provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a manufacturing method thereof.
Min Li, Min-Hwa Chi, Richard Ru-Gin Chang
Filed: 18 Jun 21
Utility
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6 Oct 22
A Cu interconnect having a diffusion barrier formed with the self-formed high-entropy alloy a method of preparing the same are provided.
Yong ZHAO, Zhaosheng MENG, Min-Hwa CHI
Filed: 23 Mar 22
Utility
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6 Oct 22
The present invention provides a mark of wafer alignment, a manufacturing method, a wafer alignment system and a method of aligning wafer.
Min-Hwa CHI
Filed: 29 Mar 22
Utility
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6 Oct 22
The present invention provides a device having a trench gate structure and a method of making the same.
Conghui LIU, Peng LI, Min-Hwa CHI
Filed: 29 Mar 22
Utility
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4 Oct 22
The present application provides a LDMOS transistor having a floating vertical field plate (VFP) and a manufacturing method thereof.
Min-Hwa Chi, Min Li
Filed: 7 Sep 21
Utility
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27 Sep 22
The present invention provides a trench gate structure and a method of forming the same.
Min-Hwa Chi, Longkang Yang, Huaihua Xu, Huan Wang, Richard Ru-Gin Chang
Filed: 28 Apr 21
Utility
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4 Aug 22
The present invention relates to an ALD (Atomic layer deposition) apparatus and an ALD method.
Zhaosheng MENG, Zhuangzhuang WU, Min-Hwa CHI
Filed: 28 Jan 22
Utility
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4 Aug 22
The present invention relates to a method of forming contact holes of a CMOS device and a method of making a CMOS device.
Min-Hwa CHI, Zhaosheng MENG, Xian ZHANG
Filed: 25 Jan 22
Utility
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26 Jul 22
This invention provides a three-dimensional junctionless neuron network device and a manufacturing method thereof.
Deyuan Xiao
Filed: 6 Nov 20
Utility
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30 Jun 22
The present application provides methods for manufacturing BiCMOS device and the heterojunction bipolar transistor (HBT) contained therein.
Min-Hwa CHI, Richard Ru-Gin CHANG
Filed: 1 Nov 21
Utility
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30 Jun 22
This invention provides a multi-Vt vertical power device and a method of making the same.
Min-Hwa CHI, Jinpeng QIU, Dongyang ZHOU, Peng LI, Conghui LIU
Filed: 15 Nov 21
Utility
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30 Jun 22
The invention provides a multi-Vt vertical power device and a method of making the same.
Min-Hwa CHI, Dongyang ZHOU, Jinpeng QIU, Peng LI, Conghui LIU
Filed: 15 Nov 21
Utility
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31 Mar 22
The present application provides a LDMOS transistor having a floating vertical field plate (VFP) and a manufacturing method thereof.
Min-Hwa CHI, Min LI
Filed: 7 Sep 21
Utility
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24 Mar 22
The present invention provides a heterojunction bipolar transistor and a method of making the same, applying fin replacement technology, fins are formed on a substrate, a well region served as a collector region is formed in the substrate, and a bottom of the fins connects to the well region served as the collector.
Min-Hwa CHI, Richard Ru-Gin CHANG
Filed: 30 Aug 21
Utility
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23 Dec 21
The present invention provides a high voltage semiconductor device comprising a combined junction terminal protection structure with a ferroelectric material and method of making the same, the device comprises: an active area formed with the high voltage semiconductor device; a combined junction terminal protection structure having a RESURF (Reduced Surface Field) structure, the RESURF structure comprising a first biasing field plate electrically connecting to the active area and a ferroelectric material layer positioned below the first biasing field plate and in contact with the first biasing field plate.
Min-Hwa CHI, Min LI, Richard Ru-Gin CHANG
Filed: 18 Jun 21
Utility
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23 Dec 21
Min LI, Min-Hwa CHI, Richard Ru-Gin CHANG
Filed: 18 Jun 21