107 patents
Page 5 of 6
Utility
MULTI-PHASE TOPOLOGY SYNTHESIS OF A NETWORK-ON-CHIP (NoC)
1 Jul 21
A process is disclosed that automatically creates a network-on-chip (NoC) very quickly using a set of constraints, which are requirements for the NoC.
Moez CHERIF, Benoit de LESCURE
Filed: 9 Dec 20
Utility
System and Method for Advanced Detection of Failures In a Network-on-chip
17 Jun 21
System and method are disclosed to detect potential failures in a network-on-chip (NoC) before the potential failures happen.
Jean-Philippe LOISON, Benoit De LESCURE
Filed: 17 Dec 19
Utility
System and Method for Transaction Broadcast In a Network on Chip
20 May 21
Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses.
Syed Ijlal SHAH, John CODDINGTON, Benoit de LESCURE
Filed: 15 Nov 19
Utility
System and method for incremental topology synthesis of a network-on-chip
27 Apr 21
Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC).
Moez Cherif, Benoit De Lescure
Filed: 27 Dec 19
Utility
System and Method for Using a Directory to Recover a Coherent System from an Uncorrectable Error
25 Mar 21
A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system.
Parimal GAIKWAD
Filed: 3 Dec 20
Utility
System for Memory Access Bandwidth Management Using Ecc
18 Mar 21
A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth.
Parimal GAIKWAD
Filed: 27 Nov 20
Utility
System and method for predicting performance, power and area behavior of soft IP components in integrated circuit design
16 Mar 21
A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP.
Benny Winefeld
Filed: 15 Nov 19
Utility
System and method for isolating faults in a resilient system
26 Jan 21
A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit.
Benoit de Lescure, Alexis Boutiller
Filed: 13 Dec 18
Utility
Recovery of a coherent system in the presence of an uncorrectable error
28 Dec 20
A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system.
Parimal Gaikwad
Filed: 27 Dec 17
Utility
System and method for reducing ECC overhead and memory access bandwidth
14 Dec 20
A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth.
Parimal Gaikwad
Filed: 21 Sep 17
Utility
System and method for designing a chip floorplan using machine learning
12 Oct 20
A system and method for estimating a floorplan designs based on feedback to machine learning algorithms to accumulate data for improving future floorplan design estimates and reducing design time.
Manadher Kharroubi
Filed: 1 Nov 18
Utility
Synthesizing topology for an interconnect network of a system-on-chip with intellectual property blocks
20 Jul 20
A SoC interconnect network topology is represented.
Raul A. Garibay, Jr., Manadher Kharroubi
Filed: 29 Dec 17
Utility
Configurable Snoop Filters for Cache Coherent Systems
8 Jul 20
A cache coherent system includes a directory with more than one snoop filter, each of which stores information in a different set of snoop filter entries.
Craig Stephen FORREST, David A. KRUCKEMYER
Filed: 17 Mar 20
Utility
SYSTEM AND METHOD FOR COMPUTATIONAL TRANSPORT NETWORK-ON-CHIP (NoC)
1 Jul 20
A system and method are disclosed for performing operations on data passing through the network to reduce latency.
Jeffrey L. NYE
Filed: 8 Jul 19
Utility
System and Method for Reducing Silicon Area of Resilient Systems Using Functional and Duplicate Logic
1 Jul 20
A resilient system implementation in a network-on-chip with data paths being duplicated in a network translation unit.
K. Charles JANAC
Filed: 28 Dec 18
Utility
Detection and Isolation of Faults to Prevent Propagation of Faults In a Resilient System
17 Jun 20
A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit.
Alexis BOUTILLER, Benoit de LESCURE
Filed: 24 Feb 20
Utility
System and Method for Logic Functional Redundancy
20 May 20
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units.
Jean Philippe Loison, Benoit deLESCURE, Alexis BOUTILLER, Rohit BANSAL, Parimal GAIKWAD
Filed: 14 Nov 19
Utility
System and Method for Estimation of Chip Floorplan Activity
18 Mar 20
Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan.
Jonah PROBELL, Monica TANG
Filed: 23 Sep 19
Utility
Functional interconnect redundancy in cache coherent systems
16 Mar 20
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units.
Benoit deLescure, Jean Philippe Loison, Alexis Boutiller, Rohit Bansal, Parimal Gaikwad
Filed: 26 Dec 16
Utility
Protection scheme conversion
6 Jan 20
Systems-on-chip are designed with different IPs that use different data protection schemes.
Monica Tang, Xavier van Ruymbeke
Filed: 28 Dec 15