57 patents
Page 3 of 3
Utility
System and Method for Synthesis of a Network-on-chip for Deadlock-free Transformation
1 Jul 21
System and methods are disclosed for transformation of a network, such as a network-on-chip (NoC).
Moez CHERIF, Benoit de LESCURE
Filed: 11 May 20
Utility
Physically Aware Topology Synthesis of a Network
1 Jul 21
System and methods are disclosed for synthesis of network, such as a network-on-chip (NoC), to generate a network description.
Moez CHERIF, Benoit De LESCURE
Filed: 27 Dec 19
Utility
System and Method for Generating and Using Physical Roadmaps In Network Synthesis
1 Jul 21
A system and methods are disclosed that generate a physical roadmap for the connectivity of a network, such as a network-on-chip (NoC).
Moez CHERIF, Benoit de LESCURE
Filed: 25 Aug 20
Utility
System and Method for Predicting Performance, Power and Area Behavior of Soft Ip Components In Integrated Circuit Design
1 Jul 21
A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP.
Benny WINEFELD
Filed: 15 Mar 21
Utility
MULTI-PHASE TOPOLOGY SYNTHESIS OF A NETWORK-ON-CHIP (NoC)
1 Jul 21
A process is disclosed that automatically creates a network-on-chip (NoC) very quickly using a set of constraints, which are requirements for the NoC.
Moez CHERIF, Benoit de LESCURE
Filed: 9 Dec 20
Utility
System and Method for Advanced Detection of Failures In a Network-on-chip
17 Jun 21
System and method are disclosed to detect potential failures in a network-on-chip (NoC) before the potential failures happen.
Jean-Philippe LOISON, Benoit De LESCURE
Filed: 17 Dec 19
Utility
System and Method for Transaction Broadcast In a Network on Chip
20 May 21
Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses.
Syed Ijlal SHAH, John CODDINGTON, Benoit de LESCURE
Filed: 15 Nov 19
Utility
System and Method for Using a Directory to Recover a Coherent System from an Uncorrectable Error
25 Mar 21
A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system.
Parimal GAIKWAD
Filed: 3 Dec 20
Utility
System for Memory Access Bandwidth Management Using Ecc
18 Mar 21
A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth.
Parimal GAIKWAD
Filed: 27 Nov 20
Utility
Configurable Snoop Filters for Cache Coherent Systems
8 Jul 20
A cache coherent system includes a directory with more than one snoop filter, each of which stores information in a different set of snoop filter entries.
Craig Stephen FORREST, David A. KRUCKEMYER
Filed: 17 Mar 20
Utility
SYSTEM AND METHOD FOR COMPUTATIONAL TRANSPORT NETWORK-ON-CHIP (NoC)
1 Jul 20
A system and method are disclosed for performing operations on data passing through the network to reduce latency.
Jeffrey L. NYE
Filed: 8 Jul 19
Utility
System and Method for Reducing Silicon Area of Resilient Systems Using Functional and Duplicate Logic
1 Jul 20
A resilient system implementation in a network-on-chip with data paths being duplicated in a network translation unit.
K. Charles JANAC
Filed: 28 Dec 18
Utility
Detection and Isolation of Faults to Prevent Propagation of Faults In a Resilient System
17 Jun 20
A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit.
Alexis BOUTILLER, Benoit de LESCURE
Filed: 24 Feb 20
Utility
System and Method for Logic Functional Redundancy
20 May 20
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units.
Jean Philippe Loison, Benoit deLESCURE, Alexis BOUTILLER, Rohit BANSAL, Parimal GAIKWAD
Filed: 14 Nov 19
Utility
System and Method for Estimation of Chip Floorplan Activity
18 Mar 20
Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan.
Jonah PROBELL, Monica TANG
Filed: 23 Sep 19
Utility
System and Method for Configurable Cache Ip with Flushable Address Range
18 Dec 19
A system and method are disclosed for a cache IP that includes registers that are programmed through a service port.
Mohammed KALEELUDDIN, Jean-Philipe LOISON
Filed: 16 Jun 19
Utility
System and Method for Self-healing of a Dynamic Link
18 Dec 19
A Network-on-Chip (NoC) link with an upstream bypassable narrowing serialization adapter and a downstream bypassable widening serialization adapter, which are able to heal a link, without losing throughput, by using one or a small number of sideband signals to bypass individual known-bad wires.
Jonah PROBELL, Alexis BOUTILLIER, Dee LIN, Monica TANG
Filed: 23 Jun 19