50 patents
Page 2 of 3
Utility
Synthesis of a network-on-chip (NoC) using performance constraints and objectives
20 Sep 22
Systems and methods are disclosed that implement a tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC).
Moez Cherif, Benoit De Lescure
Filed: 30 Dec 20
Utility
System and method for transaction broadcast in a network on chip
6 Sep 22
Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses.
Syed Ijlal Ali Shah, John Coddington, Benoit de Lescure
Filed: 15 Nov 19
Utility
System and method for logic functional redundancy
16 Aug 22
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units.
Jean Philippe Loison, Benoit de Lescure, Alexis Boutiller, Rohit Bansal, Parimal Gaikwad, Mohammed Khaleeluddin
Filed: 15 Nov 19
Utility
System and method for synthesis of a network-on-chip to determine optimal path with load balancing
16 Aug 22
A system, and corresponding method, is described for finding the optimal or the best set of routes from a master to each of its connected slaves, for all the masters and slaves using a Network-on-Chip (NoC).
Youcef Bourai, Syed Ijlal Ali Shah, Khaled Labib
Filed: 9 Apr 20
Utility
Generation of hardware design using a constraint solver module for topology synthesis
9 Aug 22
In accordance with various embodiments and aspects of the invention, systems and methods are disclosed that can automatically find the best legal configuration that will be optimal with respect to a given set of requirements or metrics, such as: area, timing, and power.
Federico Angiolini, Khaled Labib
Filed: 26 Dec 20
Utility
System for memory access bandwidth management using ECC
12 Jul 22
A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth.
Parimal Gaikwad
Filed: 27 Nov 20
Utility
System and method for using soft lock with virtual channels in a network-on-chip (NoC)
21 Jun 22
A system and method for soft locking on an ingress port of a networking device in a network, such as a network-on-chip (NoC).
John Coddington, Benoit de Lescure, Syed Ijlal Ali Shah, Sanjay Despande
Filed: 26 Dec 20
Utility
System and method for advanced detection of failures in a network-on-chip
5 Apr 22
System and method are disclosed to detect potential failures in a network-on-chip (NoC) before the potential failures happen.
Jean-Philippe Loison, Benoit De Lescure
Filed: 17 Dec 19
Utility
Optimization of parameters for synthesis of a topology using a discriminant function module
22 Mar 22
A tool is disclosed that includes a discriminant module.
Khaled Labib, Federico Angiolini
Filed: 26 Dec 20
Utility
Configurable snoop filters for cache coherent systems
1 Feb 22
A cache coherent system includes a directory with more than one snoop filter, each of which stores information in a different set of snoop filter entries.
Craig Stephen Forrest, David A. Kruckemyer
Filed: 31 Dec 14
Utility
System and method for interface protection
28 Dec 21
A system and method for adding interface protection to an electronic design using parameters.
John Coddington, Sylvain Meliciani, Frederic Greus, Xavier Van Ruymbeke
Filed: 9 Dec 20
Utility
Detection and isolation of faults to prevent propagation of faults in a resilient system
16 Nov 21
A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit.
Alexis Boutiller, Benoit de Lescure
Filed: 25 Feb 20
Utility
Physically aware topology synthesis of a network
14 Sep 21
System and methods are disclosed for synthesis of network, such as a network-on-chip (NoC), to generate a network description.
Moez Cherif, Benoit De Lescure
Filed: 27 Dec 19
Utility
System and method for estimation of chip floorplan activity
24 Aug 21
Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan.
Jonah Probell, Monica Tang
Filed: 24 Sep 19
Utility
Configurable snoop filters for cache coherent systems
3 Aug 21
A cache coherent system includes a directory with more than one snoop filter, each of which stores information in a different set of snoop filter entries.
Craig Stephen Forrest, David A. Kruckemyer
Filed: 18 Mar 20
Utility
System and method for computational transport network-on-chip (NoC)
3 Aug 21
A system and method are disclosed for performing operations on data passing through the network to reduce latency.
Jeffrey L. Nye
Filed: 9 Jul 19
Utility
System and method for incremental topology synthesis of a network-on-chip
27 Apr 21
Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC).
Moez Cherif, Benoit De Lescure
Filed: 27 Dec 19
Utility
System and method for predicting performance, power and area behavior of soft IP components in integrated circuit design
16 Mar 21
A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP.
Benny Winefeld
Filed: 15 Nov 19
Utility
System and method for isolating faults in a resilient system
26 Jan 21
A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit.
Benoit de Lescure, Alexis Boutiller
Filed: 13 Dec 18
Utility
Recovery of a coherent system in the presence of an uncorrectable error
28 Dec 20
A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system.
Parimal Gaikwad
Filed: 27 Dec 17