22699 patents
Utility
Compute-in-memory Support for Different Data Formats
18 Jan 24
Systems, apparatuses and methods include technology that identifies workload numbers associated with a workload.
Richard Dorrance, Deepak Dasalukunte, Renzhi Liu, Hechen Wang, Brent Carlton
Filed: 29 Sep 23
Utility
Apparatus and Method for Address Pre-translation to Enhance Direct Memory Access by Hardware Subsystems
18 Jan 24
Apparatus and method for performing address pre-translation to enhance direct memory access by hardware subsystems is described herein.
Kaijie GUO, Weigang LI, Junyuan WANG, Bo CUI, Mithilesh K. DAS, Amit K. WARDHAN, Zijuan FAN, Maojun JI, Qianjun XIE, Tingqiang CHU
Filed: 24 Dec 20
Utility
zuyul1flta6zkx17m1ej5f930ir zer3pubyo6ny30j7i
18 Jan 24
Circuitry for a compute-in-memory (CiM) circuit or structure arranged to detect bit errors in a group of memory cells based on a summation of binary 1's included in at least one weight matrix stored to the group of memory cells, a parity value stored to another group of memory cells and a comparison of the summation or the parity value to an expected value.
Wei WU, Hechen WANG
Filed: 25 Sep 23
Utility
9ropljaxdqw91gw4i8av6p2khys ye2ogk
18 Jan 24
Techniques and apparatus to provide for interactions between system components are described.
Kevan A. Lillie, Shlomi Lalush, Yaakov Dalsace, Adee Ofir Ran, Assaf Benhamou, David Golodni, Itay Tamir, Amir Laufer
Filed: 29 Sep 23
Utility
zm4uejog46hfkn429maw7rh0v6t13ezwf7prk
18 Jan 24
Systems, apparatuses and methods may provide for technology that includes a first check buffer to remove first intermediate partial data and first incoming partial data from a first pipeline of the first check buffer in response to a first accumulation condition in which the first intermediate partial data and the first incoming partial data share a first address in a memory, combine the first intermediate partial data and the first incoming partial data to obtain first accumulated partial data, and insert the first accumulated partial data into the first pipeline.
Kamlesh Pillai
Filed: 27 Sep 23
Utility
eg8xze6gcma3dexzllu21kd
18 Jan 24
An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes.
Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
Filed: 14 Jul 23
Utility
zlzkwsxkned3c74m50k7dkverp07ny70okaqi
18 Jan 24
Systems, apparatuses and methods may provide for technology that detects a plurality of sub-instruction requests from a first memory engine in a plurality of memory engines, wherein the plurality of sub-instruction requests are associated with a direct memory access (DMA) data type conversion request from a first pipeline, wherein each sub-instruction request corresponds to a data element in the DMA data type conversion request, and wherein the first memory engine is to correspond to the first pipeline, decodes the plurality of sub-instruction requests to identify one or more arguments, loads a source array from a dynamic random access memory (DRAM) in a plurality of DRAMs, wherein the operation engine is to correspond to the DRAM, and conducts a conversion of the source array from a first data type to a second data type in accordance with the one or more arguments.
Shruti Sharma, Robert Pawlowski, Fabio Checconi, Jesmin Jahan Tithi
Filed: 29 Sep 23
Utility
gv7humzilyt2v6h7afgiju9s8wik5l2s
18 Jan 24
Low latency neural network models are provided that can be used for speech processing.
Lukasz Pindor, Adam Kupryjanow
Filed: 26 Sep 23
Utility
ba1bjd6zlqiu0w6295b8kb y4lwys2i0r65csbz4fr49
18 Jan 24
Systems, apparatuses and methods may provide for technology that conducts a traversal of a directed graph in response to a query, retrieves the plurality of vectors from a dynamic random access memory (DRAM) in accordance with the traversal of the directed graphs, wherein each vector in the plurality of vectors is compressed, decompresses the plurality of vectors, determines a similarity between the query and the decompressed plurality of vectors, and generates a response to the query based on the similarity between the query and the decompressed plurality of vectors.
Maria Cecilia Aguerrebere Otegui, Ishwar Bhati, Mark Hildebrand, Mariano Tepper, Theodore Willke
Filed: 3 Aug 23
Utility
kdo90mbrpm0mmg 8b7h3tfd126ixsop1fl5dw
18 Jan 24
In one embodiment, an apparatus comprises a log circuit to: identify an input associated with a logarithm operation, wherein the logarithm operation is to be performed by the log circuit using piecewise linear approximation; identify a first range that the input falls within, wherein the first range is identified from a plurality of ranges associated with a plurality of piecewise linear approximation (PLA) equations for the logarithm operation, and wherein the first range corresponds to a first equation of the plurality of PLA equations; compute a result of the first equation based on a plurality of operands associated with the first equation; and return an output associated with the logarithm operation, wherein the output is generated based at least in part on the result of the first equation.
Kamlesh Pillai, Gurpreet S. Kalsi, Amit Mishra
Filed: 24 Aug 23
Utility
2m8mskiw8tnjc75pfj05cg vt5
18 Jan 24
Systems, apparatus, articles of manufacture, and methods are disclosed to improve container security.
Mikko Kalevi Ylinen, Ismo Puustinen, Malini Bhandaru
Filed: 29 Sep 23
Utility
ovd463cm4s0exelmawt7nqww0xfzeo
18 Jan 24
Embodiments described herein are generally directed to decentralized proof of creation.
Sanjay Bakshi, Gautam Singh, Geoffrey Gustafson, Muthaiah Venkatachalam
Filed: 29 Sep 23
Utility
w15j33419nzsmkcdk2mvr53msge9ubsor
18 Jan 24
Systems, apparatus, articles of manufacture, and methods are disclosed to generate and manage a firewall policy.
Akhilesh Thyagaturu, Jason Howard, Nicholas Ross, Sanjaya Tayal, Vinodh Gopal
Filed: 27 Sep 23
Utility
51fu9hw7svdqbnesrzrj8zzx1i0r37fa2vko8mmt9crmegj84au4j2
18 Jan 24
Self-test and repair of memory cells is performed in a memory integrated circuit by two separate processes initiated by a memory controller communicatively coupled to the memory integrated circuit.
Bill NALE
Filed: 27 Sep 23
Utility
9u3m3k0pyxa8zmk3kv5sl6k21nh sz1adncus286mselk2jpi
18 Jan 24
Systems, apparatuses and methods may provide for technology that determines a vocabulary based on EDA tool terminologies and/or a natural language, queries and recommends, by a plurality of virtual agents, actions based on a design state and the vocabulary, wherein the plurality of agents is to include a tool agent and a designer agent, and executes a set of modifications to the design state in accordance with a collaboration between the plurality of agents.
Siddhartha Nath, Rajeshkumar Sambandam, Uday Mallappa, Somdeb Majumdar, Mariano Phielipp, Xia Zhu, Jianfang Olena Zhu, Francisco Javier Vera Rivera, Miaomiao Ma
Filed: 29 Sep 23
Utility
23yggp49ohpq6wxo3v5rrpbmu621z7dw0v5p7hxup2f35ta794fm7fy4
18 Jan 24
Microelectronic assemblies, and related devices and methods, are disclosed herein.
Shawna M. LIFF, Adel A. ELSHERBINI, Johanna M. SWAN
Filed: 28 Sep 23
Utility
bi1shik5 zfzr5t9ghnlfq83
18 Jan 24
Systems or methods of the present disclosure may provide a library including multiple macros that may be pre-compiled prior to implementation of the design.
Byron Sinclair, Deshanand P. Singh, Gregg William Baeckler, Mahesh A. Iyer, Michael Kinsner, Chengping Liang, Victor Tzi-on Zhang
Filed: 27 Sep 23
Utility
3shlce3a8a9q697qc5pm2l9l
18 Jan 24
Methods, systems, articles of manufacture, and apparatus are disclosed to decode zero-value-compression data vectors.
Gautham Chinya, Debabrata Mohapatra, Arnab Raha, Huichu Liu, Cormac Brick
Filed: 12 Sep 23
Utility
3pswpi4nyjbrezrs6k9h2w9bq28sjh1jvqjdyq0re4h
18 Jan 24
Apparatus and method for routing data from ray tracing cache banks For example, one embodiment of an apparatus comprises: ray traversal hardware logic to perform traversal operations to traverse rays through a bounding volume hierarchy (BVH) comprising a plurality of BVH nodes, the ray traversal hardware logic comprising a plurality of traversal storage banks to store traversal data associated with the BVH nodes and/or the rays as the ray traversal hardware logic performs the traversal operations; and a cache comprising a plurality of cache banks to store the traversal data prior to being moved into the traversal storage banks for processing by the ray traversal hardware logic; and an inter-bank interconnect comprising: a point-to-point switch matrix to couple any of the cache banks to any of the traversal storage banks; an arbiter/allocator to control the point-to-point switch matrix to establish a particular group of interconnections between the cache banks and the traversal storage banks in a given clock cycle.
Michael NORRIS, Abhishek R. APPU, Prasoonkumar SURTI, Karthik VAIDYANATHAN
Filed: 26 May 22
Utility
116lwf9iol70n4fdx9fpe5inws3 mz00ty
18 Jan 24
A port of a computing device is to communicate with another device over a link, the port including physical layer logic of a first protocol, link layer logic of each of a plurality of different protocols, and protocol negotiation logic to determine which of the plurality of different protocols to apply on the link.
Debendra Das Sharma
Filed: 7 Sep 23