21162 patents
Utility
Method and Apparatus for Removing Laser Debond Residue from Substrate
21 Sep 23
A method includes forming a solvent on a stage, and placing, on the solvent formed on the stage, a bottom surface of a substrate on which a residue is formed, so that the residue moves away from the bottom surface of the substrate into the solvent.
Jeremy ECTON, Vinith BEJUGAM, Jefferson KAPLAN, Yonggang LI, Whitney BRYKS, Samuel GEORGE, Jeremy CROSS
Filed: 18 Mar 22
Utility
On-chip Digitally Controlled Error Rate-locked Loop for Error Resilient Edge Artificial Intelligence
21 Sep 23
Embodiments herein relate to a neural network processor in a control loop, where the control loop sets an optimum supply voltage for the processor based on a measured error count or rate of the neural network.
Hechen WANG
Filed: 15 Mar 22
Utility
Non-destructive Gap Metrology
21 Sep 23
The present disclosure is directed to a metrology system having 3-dimensional sensors for thickness measurements of semiconductor elements, and methods for taking the thickness measurements.
Jianyong MO, V Wade SINGLETON, Yiren WU, Liang ZHANG, David WASINGER
Filed: 17 Mar 22
Utility
Granular Gpu DVFS with Execution Unit Partial Powerdown
21 Sep 23
Described herein, in one embodiment, are techniques to facilitate the partial powerdown of sub-components of an execution unit or other graphics processing resource based on the workload to be executed.
Kenneth Daxer, Stephen H. Gunther, Michael N. Derr, Eric Samson
Filed: 16 Mar 23
Utility
Fused Multiple Multiplication and Addition-subtraction Instruction Set
21 Sep 23
An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused multiple multiplication and addition-subtraction operation, and execution circuitry to execute the decoded instruction according to the opcode to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused multiple multiplication and addition-subtraction indicated by the opcode on four or more arguments indicated by the retrieved data to produce one or more results.
Fabian Boemer, Vinodh Gopal
Filed: 15 Mar 22
Utility
Instruction and Logic for Systolic Dot Product with Accumulate
21 Sep 23
Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations.
SUBRAMANIAM MAIYURAN, GUEI-YUAN LUEH, SUPRATIM PAL, ASHUTOSH GARG, CHANDRA S. GURRAM, JORGE E. PARRA, JUNJIE GU, KONRAD TRIFUNOVIC, HONG BIN LIAO, MIKE B. MACPHERSON, SHUBH B. SHAH, SHUBRA MARWAHA, STEPHEN JUNKINS, TIMOTHY R. BAUER, VARGHESE GEORGE, WEIYU CHEN
Filed: 26 Apr 23
Utility
Multiple Operation Fused Addition and Subtraction Instruction Set
21 Sep 23
An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused addition and subtraction operation, and execution circuitry to execute the decoded instruction according to the opcode to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused addition and subtraction operation indicated by the opcode on three or more arguments indicated by the retrieved data to produce one or more results.
Fabian Boemer, Vinodh Gopal
Filed: 15 Mar 22
Utility
Hard Partitioning Via Intra-soc Composition
21 Sep 23
Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains.
David Cowperthwaite, Kenneth Daxer, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Hema Chand Nalluri, Jeffery S. Boles, Vasanth Ranganathan, Joydeep Ray, David Puffer, Aravindh Anantaraman, Ankur Shah, Vidhya Krishnan, Kritika Bala, Michael Apodaca
Filed: 27 May 22
Utility
Device Virtualization In a Confidential Computing Environment
21 Sep 23
Examples described herein relate to a trusted and secure emulated device.
Kapil SOOD, Scott P. DUBAL, Patrick CONNOR, James R. HEARN
Filed: 22 May 23
Utility
Flexible Partitioning of Gpu Resources
21 Sep 23
Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources.
David Cowperthwaite, Kenneth Daxer, Jeffery S. Boles, Hema Chand Nalluri, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Vasanth Ranganathan, Joydeep Ray, David Puffer, Aravindh Anantaraman, Ankur Shah, Vidhya Krishnan, Kritika Bala
Filed: 27 May 22
Utility
Apparatus and Method for Scheduling Inference Tasks
21 Sep 23
Apparatus and method for scheduling inference tasks.
PAWEL MAJEWSKI, PRASOONKUMAR SURTI, TOBIAS ZIRR
Filed: 18 Mar 22
Utility
Scalable I/o Virtualization Interrupt and Scheduling
21 Sep 23
Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor.
David Puffer, Ankur Shah, Niranjan Cooray, Bryan White, Balaji Vembu, Hema Chand Nalluri, Kritika Bala
Filed: 3 Jun 22
Utility
Load Store Bank Aware Thread Scheduling Techniques
21 Sep 23
Bank aware thread scheduling and early dependency clearing techniques are described herein.
Abhishek R. APPU, Joydeep RAY, Karthik VAIDYANATHAN, Sreedhar CHALASANI, Vasanth RANGANATHAN
Filed: 21 Mar 22
Utility
Rollback of Processor Microcode Updates In Runtime without System Reboot
21 Sep 23
Techniques for updates and rollbacks of firmware patches in a computing system during runtime are provided.
Pratim Bose, Karunakara Kotary, Kausik Ghosh, Arun Hodigere
Filed: 15 Mar 22
Utility
System, Apparatus and Method for Providing Hardware State Feedback to an Operating System In a Heterogeneous Processor
21 Sep 23
In one embodiment, a processor includes a power controller having a resource allocation circuit.
Praveen Kumar Gupta, Avinash N. Ananthakrishnan, Eugene Gorbatov, Stephen H. Gunther
Filed: 24 May 23
Utility
Enabling Secure State-clean During Configuration of Partial Reconfiguration Bitstreams on Fpga
21 Sep 23
An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed.
Alpa Trivedi, Scott Weber, Steffen Schulz, Patrick Koeberl
Filed: 14 Apr 23
Utility
Apparatus and Method for Hardware-accelerated Texture Lookup and Interpolation
21 Sep 23
Embodiments of the invention include acceleration hardware for performing texture lookups and for interpolation for textures backed by hashed memory layouts.
TOBIAS ZIRR, CARSTEN BENTHIN
Filed: 18 Mar 22
Utility
Multi-render Partitioning
21 Sep 23
Described herein is a partitionable graphics processor having multiple render front ends.
Hema Chand Nalluri, Jeffery S. Boles, David Cowperthwaite, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Vasanth Ranganathan, Joydeep Ray, David Puffer, Ankur Shah, Vidhya Krishnan, Kritika Bala, Aravindh Anantaraman, Michael Apodaca, Kenneth Daxer
Filed: 27 May 22
Utility
Cache Streaming Apparatus and Method for Deep Learning Operations
21 Sep 23
A cache streaming apparatus and method for machine learning.
Prasoonkumar SURTI, Tobias ZIRR, Abhishek R. APPU, Anton KAPLANYAN, Pawel MAJEWSKI, Joshua BARCZAK
Filed: 18 Mar 22
Utility
Local Memory Translation Table
21 Sep 23
Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain.
David Puffer, Ankur Shah, Niranjan Cooray, Aditya Navale, David Cowperthwaite
Filed: 24 Jun 22