20858 patents
Page 16 of 1043
Utility
Enhancing Video Language Learning by Providing Catered Context Sensitive Expressions
14 Dec 23
A computer processing system is provided for enhancing video-based language learning.
I-Hsiang Liao, Cheng-Yu Yu, Chih-Yuan Lin, Yu-Ning Hsu
Filed: 16 Aug 23
Utility
Generating Multi-turn Dialog Datasets
14 Dec 23
An embodiment for generating multi-turn dialog datasets for training of dialog or conversational agents.
Zilu Tang, Zhongshen zeng, Yara Rizk
Filed: 8 Jun 22
Utility
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14 Dec 23
A method, a computer program product, and a computer system determine a name of an individual based on voice detection.
ETHAN S. HEADINGS, Feng-wei Chen, Neha S. Deshpande, Madhavi Kolachala
Filed: 10 Jun 22
Utility
9i7093yib31n15z55vn08s98tdlf14682h229mjo0oevo8nkvea
14 Dec 23
A memory device includes a magnetic tunnel junction (MTJ) pillar between a top electrode and a bottom electrode.
Oscar van der Straten, Koichi Motoyama, Chih-Chao Yang
Filed: 13 Jun 22
Utility
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14 Dec 23
Embodiments of the invention include a semiconductor structure with a first magneto-resistive random access memory (MRAM) pillar with a bottom electrode layer, a reference layer connected above the bottom electrode layer, a free layer, and a tunnel barrier between the reference layer and the free layer.
Oscar van der Straten, Koichi Motoyama, Chih-Chao Yang
Filed: 14 Jun 22
Utility
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14 Dec 23
A semiconductor structure including a middle-of-line contact, a backside power rail, and a contact via extending between the middle-of-line contact and the backside power rail, wherein the contact via comprises a first portion having a negative tapered profile and a second portion having a positive tapered profile.
Ruilong Xie, Kisik Choi, SOMNATH GHOSH, Julien Frougier, Stuart Sieg, Kevin Shawn Petrarca
Filed: 10 Jun 22
Utility
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14 Dec 23
A semiconductor component includes an area of dielectric material extending below an uppermost surface of a substrate.
Sagarika Mukesh, Devika Sarkar Grant, FEE LI LIE, Hosadurga Shobha, Thamarai selvi Devarajan, Aakrati Jain
Filed: 13 Jun 22
Utility
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14 Dec 23
Provided is a semiconductor device.
Tao Li, Kisik Choi, Albert M. Young, Julien Frougier, Ruilong Xie
Filed: 13 Jun 22
Utility
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14 Dec 23
A skip-level through-silicon via structure is provided that enables low resistance via connection for backside power distribution by skipping one or more intermediate backside metal layers.
Nicholas Anthony Lanzillo, Ruilong Xie, Huai Huang, Hosadurga Shobha, Lawrence A. Clevenger
Filed: 10 Jun 22
Utility
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14 Dec 23
An approach provides a semiconductor structure with one or more rectangular or square-shaped contact vias in a semiconductor material.
Kangguo Cheng, Ruilong Xie, Julien Frougier, Min Gyu Sung, CHANRO PARK
Filed: 13 Jun 22
Utility
0lb92h15pnl08cycr4t8bows9v853ujr63hs8juou2c2ji28vbusrd5bpzs
14 Dec 23
A semiconductor device is provided.
Brent A. Anderson, Ruilong Xie, Albert M. Young, Albert M. Chu
Filed: 10 Jun 22
Utility
xiunji3vw5q5dym58jq3ad9opqc4tdqdwtvd w3mzuag7iw0vqs9babe
14 Dec 23
A semiconductor device is provided.
Sanjay C. Mehta, Ruilong Xie, Shogo Mochizuki, Min Gyu Sung
Filed: 10 Jun 22
Utility
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14 Dec 23
A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region.
Ruilong Xie, Chen Zhang, Julien Frougier, Alexander Reznicek, SHOGO MOCHIZUKI
Filed: 10 Aug 23
Utility
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14 Dec 23
A semiconductor device and formation thereof.
Min Gyu Sung, Ruilong Xie, Heng Wu, Julien Frougier
Filed: 10 Jun 22
Utility
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14 Dec 23
An apparatus comprises one or more A-type resistance segments, wherein each A-type resistance segment comprises one or more A-type switches, at least one A-type linear resistor coupled to the one or more A-type switches, at least one A-type tunable header unit coupled to the one or more A-type switches, and at least one A-type tunable footer unit coupled to the one or more A-type switches; one or more B-type resistance segments, wherein each B-type resistance segment comprises one or more B-type switches, at least one B-type linear resistor coupled to at least a proper subset of the one or more B-type switches, at least one B-type tunable header unit coupled to the one or more B-type switches, and at least one B-type tunable footer unit coupled to the one or more B-type switches; and wherein second terminals of the A-type linear resistors and the B-type linear resistors are coupled together.
Martin Cochet, Marcel A. Kossel, John Francis Bulzacchelli, Timothy O. Dickson, Zeynep Toprak-Deniz
Filed: 13 Jun 22
Utility
ii2aqndhy7zg45885duaedyyu40l81qxh7n4k
14 Dec 23
An example system includes a processor to receive a machine learning network and a selected homomorphic encryption (HE) packing framework.
Nir DRUCKER, Moran BARUCH
Filed: 13 Jun 22
Utility
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14 Dec 23
A method, a computer program product, and a system are provided that handles host requests on a hardware security module (HSM).
Surya V. Duggirala, Richard Victor Kisley, Mark Douglas Marik, Michael Ordway Tingey, JR.
Filed: 13 Jun 22
Utility
d0i0jckl1ahrg9uw5mccggvojapuq9myg804xd
14 Dec 23
A system may prove one or more attributes of a user by generating cyclic groups, generating an aggregate anonymous credential by a regulatory authority and issuers of the system, setting up an issuer with a multi-signature of administrators of the system, generating user credentials, and validating an operation signed with the user credentials.
Kaoutar El Khiyaoui, Angelo De Caro, Elli Androulaki
Filed: 8 Jun 22
Utility
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14 Dec 23
A memory device includes a magnetic tunnel junction pillar extending vertically from a bottom electrode.
Oscar van der Strate, Koichi Motoyama, Chih-Chao Yang
Filed: 14 Jun 22
Utility
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14 Dec 23
A magnetic tunnel junction (MTJ) stack, a vertical side surface of the MTJ stack includes a saw tooth edge, the MTJ stack includes vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, the free layer of the MTJ stack has a tapered edge including a first width at an upper portion of the free layer and a second width at a lower portion of the free layer, the first width is greater than the second width.
Koichi Motoyama, Oscar van der Straten, Chih-Chao Yang
Filed: 13 Jun 22