61485 patents
Page 12 of 3075
Utility
Apparatus and method for estimating analyte concentration
16 Jan 24
A method of estimating a concentration of an analyte may include obtaining a plurality of in vivo estimation spectra, generating a plurality of noise detection models by varying a number of principal components based on the plurality of in vivo estimation spectra, comparing the generated plurality of noise detection models with a plurality of concentration estimation models for each number of principal components, extracting a noise spectrum and a concentration estimation model for use in estimating the concentration of the analyte based on the comparison, updating the extracted concentration estimation model based on the extracted noise spectrum, and estimating the concentration of the analyte by using the updated concentration estimation model and an in vivo estimation spectrum from among the plurality of in vivo estimation spectra.
Sang Kon Bae, So Young Lee
Filed: 13 Jan 20
Utility
Air cleaner
16 Jan 24
An operation mode of an air cleaner is changed according to the degree of indoor air contamination and an indoor space condition, and one or more filters of the air cleaner can be easily cleaned.
Young Seok Lee, Dah We Park, Ji Hyeoung Lee, Tim Rochford
Filed: 20 Jun 17
Utility
3q9jt0qvtak36213stpr4m0pr3v0qe037gyv2
16 Jan 24
According to various embodiments, an electronic apparatus comprises: a housing including a first plate, a second plate facing in the opposite direction as the first plate, and side members surrounding the space between the second plate and the second plate; a printed circuit board which is disposed within the space and on which at least one electrical component is mounted; a shield can mounted on the printed circuit board and disposed to surround the at least one electrical component; and an insulating tape member attached to the inner surface of the shield can between the shield can and the electrical component.
Daum Hwang, Sangin Baek
Filed: 29 May 19
Utility
baqh5cdg3ju38veztog12qrh5zjgi1j80xjet8sl33tmdcfqu8oom9
16 Jan 24
Semiconductor devices are provided.
Hyun-Suk Lee, Jungoo Kang, Gihee Cho, Sanghyuck Ahn
Filed: 28 Jun 22
Utility
y9rt4oz7w4doqt0ey2936g4gcj7ueo9ye19al7bgt1i1i
16 Jan 24
Integrated circuit devices and methods of forming the same are provided.
Tae Yong Bae, Hoon Seok Seo, Ki Hyun Park, Hak-Sun Lee
Filed: 15 Dec 21
Utility
0w9ja8qcaiup12b0efzxz0o9
16 Jan 24
Semiconductor devices and methods of forming the semiconductor devices are provided.
Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
Filed: 10 Nov 21
Utility
houveky7tsxe376t9j2ds7c96k7q43n7pl6akh
16 Jan 24
A semiconductor package includes at least one semiconductor device mounted on a first substrate, a thermosetting resin layer on the at least one semiconductor device, the thermosetting resin layer including an irreversible thermochromic pigment, a metal plate on the thermosetting resin layer, and a molding member surrounding the at least one semiconductor device at least in a lateral direction and being in contact with the thermosetting resin layer.
Joungphil Lee, Wonkeun Kim, Mihyae Park
Filed: 15 Jul 21
Utility
zdxhpu37fr50mcd56b796eduh7h6q0ygi06i4glk9ez9gc
16 Jan 24
A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer.
Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
Filed: 8 Sep 21
Utility
hdvo26jbgi65e5f87 1zduhfn
16 Jan 24
A semiconductor device includes a substrate having a chip region and a scribe lane region having first edges extending in a first direction and second edges extending in a second direction, a first insulating interlayer structure on the scribe lane region and including a low-k dielectric material, first conductive structures on a portion of the scribe lane region adjacent one of the first edges and each extending through the first insulating interlayer structure in a vertical direction and extending in the first direction, a second insulating interlayer on the first insulating interlayer structure and including a material having a dielectric constant greater than that of the first insulating interlayer structure, first vias each extending in the first direction through the second insulating interlayer to contact one of the first conductive structures, and a first wiring commonly contacting upper surfaces of the first vias.
Jooncheol Kim, Sangwoo Hong
Filed: 4 May 20
Utility
25iplk40lpsfnfk7ttsqdk0ja3l3tt5t47eglnlx
16 Jan 24
Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.
Dongho Kim, Ji Hwang Kim, Hwan Pil Park, Jongbo Shim
Filed: 20 Aug 21
Utility
vnfk5lltn4q9pfwktbah8nbirws97aqhbyppz9pzwyz0 q0l7
16 Jan 24
A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.
Krishna Kumar Bhuwalka, Kyoung Min Choi, Takeshi Okagaki, Dong Won Kim, Jong Chol Kim
Filed: 6 Aug 21
Utility
spg0ao1uw2wd129g3x54618bpym mz
16 Jan 24
Provided is a display device including a substrate, a transfer guiding mold provided on the substrate and including a plurality of openings, and a plurality of micro light emitting diodes (LEDs) provided on the substrate in the plurality of openings, wherein a height of the transfer guiding mold is less than twice a height of each of the plurality of micro LEDs.
Kyungwook Hwang, Sungjin Kang, Junsik Hwang, Junhee Choi
Filed: 24 Jan 22
Utility
6ikk3dclg8xkch0bmznlu6krpb12ky2nd9fyrhwp2hd5r8sh
16 Jan 24
KyuJung Jun, Gerbrand Ceder, Yan Wang, Lincoln Miara, Yan Zeng, Yihan Xiao
Filed: 17 May 21
Utility
7cb3pw9zinhm7qvkgpiiomvipxqzxwadzktz0env 4km5fw
16 Jan 24
The present invention relates to an electrical connection device and an electronic device comprising same, wherein a receptacle includes a plurality of conductive terminals that are arranged to press a connector in different directions and induces stable contact when the connector is connected to the receptacle.
Inha Lee, Seoungho Jung, Hanseok Mun, Jaeryong Han
Filed: 18 Oct 19
Utility
sxzkmgovfg8o7glls4tqm72zhl28t1r6ukemxrhew89dn5pvplic6
16 Jan 24
A DC-DC converter including a switching buck regulator including a first power switch connected to a first power node, a second power switch connected to a second power node, a driver configured to drive the first and second power switches, an output filtering inductor connected to a node between the first and second power switches, and an output filtering capacitor connected to the output filtering inductor, a controller configured to compensate for an output signal of the switching buck regulator in a time domain using a reference voltage, and a feed forward circuit connected between the switching buck regulator and the controller, and including a first buffer, a second buffer, an RC filter, and an adder may be provided.
Jeongpyo Park, Taehwang Kong, Junhyeok Yang, Donghoon Jung
Filed: 17 Sep 21
Utility
1rb1be93u85rc6xjlidwzo9n2jjc9sj9quxn5x
16 Jan 24
An oscillator includes a crystal oscillation circuit configured to generate an oscillation signal having a natural frequency, an injection circuit configured to inject a first injection signal and a second injection signal into the crystal oscillation circuit, a dithering circuit configured to transmit a first control signal for generating the first injection signal to the injection circuit, and a phased-lock loop (PLL) circuit configured to lock a phase of the first injection signal to the natural frequency, to transmit a second control signal for generating the second injection signal to the injection circuit.
Jaehong Jung, Seungjin Kim, Seunghyun Oh
Filed: 10 Jan 23
Utility
9omve30lfqqq j61gy3clejyy47lr2o7utui
16 Jan 24
Embodiments herein provide a method for predicting iterations for decoding an encoded data at an electronic device.
Anusha Gunturu, Ashok Kumar Reddy Chavva, Avani Agrawal, Saikrishna Pedamalli, Satya Kumar Vankayala, Anshuman Nigam, Mohan Rao Naga Santha Goli
Filed: 19 May 22
Utility
221rkezwf78vdf6ouam3qcaopgdzvhvpr5acns
16 Jan 24
A method may include, and/or a device may be configured for: receiving, from a transmitting device, a signal corresponding to input bits; performing demodulation based on the signal to determine values corresponding to the input bits; identifying a number of the input bits based on the signal; identifying a base matrix and a lifting size based on the number of the input bits; identifying a parity check matrix based on the base matrix; determining a number of layers based on the lifting size and a number of the values; determining an order of layers for low density parity check (LDPC) decoding based on the number of layers; and performing the LDPC decoding to determine the input bits based on the values, the parity check matrix, and the order of layers.
Seho Myung, Min Jang, Yangsoo Kwon, Jeongho Yeo, Hongsil Jeong
Filed: 15 Nov 21
Utility
lm8rrhki3uo3870tku801o8z2sj0owuj0d58enqumr9
16 Jan 24
The present invention relates to a method for transmitting a packet in a communication system, the method comprising: generating drop information indicating at least one source packet to be dropped among source packets to be transmitted and whether or not to drop each of the other source packets except the at least one source packet; performing forward error correction (FEC) encoding on the drop information and the other source packets except the at least one source packet; generating a repair packet comprising repair data for restoring the drop information and a repair symbol for restoring the other source packets except the at least one source packet; and transmitting the other source packets except the at least one source packet and the repair packet.
Sung-Hee Hwang, Hyun-Koo Yang
Filed: 18 Oct 22
Utility
dy0tiun5s7jyexjwem8vsh8kxfqw6wn6hs9gxf2xakz
16 Jan 24
A method and apparatus are provided for wireless communication between a base station and a user equipment (UE).
Hoda Shahmohammadian, Jung Hyun Bae, Jungwon Lee
Filed: 25 May 21