Exhibit 99.2
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investor meeting
2015 SANTA CLARA
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Advancing moore’s law
Bill Holt
Executive Vice President
General Manager, Technology and Manufacturing Group
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Agenda
Progress
14nm Update
Cost per Transistor Trend
Economics of Moore’s Law
– What does it take to afford to continue?
Competitiveness
Forward looking options
3
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14 nm Product Yield Is In Healthy Range
14nm Broadwell Yield Trend
Increasing Yield
Investor Meeting 2014
22nm Is Intel’s Highest Yielding Process Ever
22 nm data are shifted to align date of lead product qual
4
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14 nm Yield Is Maturing
1H’14 2H‘14 1H’15 2H’15 1H’16
22 nm data are shifted to align date of lead product qual
Trending to match 22nm yields
Source: Intel
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Cost per Transistor Trend
100
10
1
0.1
X
0.01
1
0.1
+
0.01
$ / mm2 (normalized) mm2 / Transistor (normalized) $ / Transistor (normalized)
Source: Intel estimate, based upon available information and subject to change
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Agenda
Progress
14nm Update
Cost per Transistor Trend
Economics of Moore’s Law
– What does it take to afford to continue?
Competitiveness
Forward looking options
7
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Moore’s Law Enables Innovation and Cost Reductions
32nm 22nm 14nm 10nm 7nm 5nm
Twice the
Same circuitry circuitry in the Option to design half the space OR same space = for optimal (cost reduction) (architectural performance/cost innovation)
Source: Intel
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AdvancING Process Technology Lowers Costs
Ten Year Model of Manufacturing and Process R & D
$302B
2011 Analysis
Same ten process years for
$104B
Process R & D
Develop processes new
Manufacturing Costs
Assumptions are theoretical and not forecasts.
Source: Intel
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AdvancING Process Technology Lowers Costs
Ten Year Model of Manufacturing and Process R & D
2015 Update $270B Same ten process years for
$116B
Process R & D
Develop processes new
Manufacturing Costs
Assumptions are theoretical and not forecasts.
Source: Intel
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Three Ways To Test the Model:
Lower unit demand
Higher technology development cost
Reduced cost per transistor improvement
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Three Ways To Test THE Model: Unit Demand changes
Assumptions are theoretical and not forecasts
Source: Intel
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Three Ways To Test THE Model: R&D cost Increases
Higher R&D investment growth will NOT limit Moore’s Law
Assumptions are theoretical and not forecasts.
Source: Intel
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Three Ways To Test THE Model: CPT improvement reduces
1.0
Per
Cost CPT~0.86
Reduction
Normalized Transistor CPT~0.69x 0.1
65nm 45nm 32nm 22nm 14nm 10nm Historical CPT 14nm/10nm Overscaling BE CPT
Poorer CPT scaling could challenge economic benefits
Assumptions are theoretical and not forecasts
Source: Intel
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Agenda
Progress
14nm Update
Cost per Transistor Trend
Economics of Moore’s Law
– What does it take to afford to continue?
Competitiveness
Forward looking options
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Logic Area Scaling Trend (Publicly available scaling information)
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ESTIMATED FULL CHIP SCALING
Area scaling estimate includes more of the technology features
Sources: TSMC keynote, ARM Tech Con 2012, Oct. 30, 2012, 2014 TSMC Technology Symposium, April 22, 2014, Samsung, Globalfoundries Prep 14nm Process, EE Times 4/17/2014, 2014.
2014 VLSI Technology Symposium abstract—A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI, Samsung, Global Foundries, et. al. Intel: P1274/P1275 Definition Wrap-up, TMG Technology Density working group, * Projected Other names and brands may be claimed as the property of others.
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TRANSISTOR DENSITY FROM ACTUAL PRODUCTS
Source: Intel Internal analysis
Other names and brands may be claimed as the property of others.
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Composition Matters
Source: Intel Internal analysis
Other names and brands may be claimed as the property of others.
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TRANSISTOR DENSITY NORMALIZED FOR COMPOSITION
Source: Intel Internal analysis
Other names and brands may be claimed as the property of others.
Source: Intel internal analysis
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FULL CHIP SCALING UPDATED WITH ACTUAL 14/16NM PRODUCTS
Intel 14nm provides significant density advantage
Sources: TSMC keynote, ARM Tech Con 2012, Oct. 30, 2012, 2014 TSMC Technology Symposium, April 22, 2014, Samsung, Globalfoundries Prep 14nm Process, EE Times 4/17/2014, 2014.
2014 VLSI Technology Symposium abstract—A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI, Samsung, Global Foundries, et. al. Intel: P1274/P1275 Definition Wrap-up, TMG Technology Density working group, * Projected Other names and brands may be claimed as the property of others.
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Future Options Being Investigated
High RF, mm-Wave Voltage
HETEROGENEOUS INTEGRATION
Sensors/Actuators SELECTIVE
Quantum DEPOSITION
FUNCTION INTEGRATION SYSTEM DIRECTED SELF-ASSEMBLY
Flexible/Stretchable
RRAM and STTM Nanowire Tunnel FET III-V III-V Spin-based
SCALING Source: Intel
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Summary
14nm yields, availability and product portfolio MATURING
Cost per Transistor is difficult, but progress is PROMISING
Economics of Moore’s Law for Intel are SOLID
Our view of competition is UNCHANGED
Innovation and change will be required looking forward but….
The research pipeline is challenging but FULL
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investor meeting
2015 SANTA CLARA
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Risk Factors
The statements in this presentation and other commentary that refer to future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “goals,” “plans,” “believes,” “seeks,” “estimates,” “continues,” “may,” “will,” “should,” and variations of such words and similar expressions are intended to identify such forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Many factors could affect Intel’s actual results, and variances from Intel’s current expectations regarding such factors could cause actual results to differ materially from those expressed in these forward-looking statements. Intel presently considers the following to be important factors that could cause actual results to differ materially from the company’s expectations. Demand for Intel’s products is highly variable and could differ from expectations due to factors including changes in business and economic conditions; consumer confidence or income levels; the introduction, availability and market acceptance of Intel’s products, products used together with Intel products and competitors’ products; competitive and pricing pressures, including actions taken by competitors; supply constraints and other disruptions affecting customers; changes in customer order patterns including order cancellations; and changes in the level of inventory at customers. Intel’s gross margin percentage could vary significantly from expectations based on capacity utilization; variations in inventory valuation, including variations related to the timing of qualifying products for sale; changes in revenue levels; segment product mix; the timing and execution of the manufacturing ramp and associated costs; excess or obsolete inventory; changes in unit costs; defects or disruptions in the supply of materials or resources; and product manufacturing quality/yields. Variations in gross margin may also be caused by the timing of Intel product introductions and related expenses, including marketing expenses, and Intel’s ability to respond quickly to technological developments and to introduce new products or incorporate new features into existing products, which may result in restructuring and asset impairment charges. Intel’s results could be affected by adverse economic, social, political and physical/infrastructure conditions in countries where Intel, its customers or its suppliers operate, including military conflict and other security risks, natural disasters, infrastructure disruptions, health concerns and fluctuations in currency exchange rates. Results may also be affected by the formal or informal imposition by countries of new or revised export and/or import and doing-business regulations, which could be changed without prior notice. Intel operates in highly competitive industries and its operations have high costs that are either fixed or difficult to reduce in the short term. The amount, timing and execution of Intel’s stock repurchase program could be affected by changes in Intel’s priorities for the use of cash, such as operational spending, capital spending, acquisitions, and as a result of changes to Intel’s cash flows or changes in tax laws. Product defects or errata (deviations from published specifications) may adversely impact our expenses, revenues and reputation. Intel’s results could be affected by litigation or regulatory matters involving intellectual property, stockholder, consumer, antitrust, disclosure and other issues. An unfavorable ruling could include monetary damages or an injunction prohibiting Intel from manufacturing or selling one or more products, precluding particular business practices, impacting Intel’s ability to design its products, or requiring other remedies such as compulsory licensing of intellectual property. Intel’s results may be affected by the timing of closing of acquisitions, divestitures and other significant transactions. In addition, risks associated with our pending acquisition of Altera are described in the “Forward Looking Statements” paragraph of Intel’s press release dated June 1, 2015, which risk factors are incorporated by reference herein. A detailed discussion of these and other factors that could affect Intel’s results is included in Intel’s SEC filings, including the company’s most recent reports on Form 10-Q, Form 10-K and earnings release.
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