107 patents
Utility
Galvanic isolation using isolation break between redistribution layer electrodes
17 Oct 23
A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode.
Bong Woong Mun, Wanbing Yi, Juan Boon Tan, Jeoung Mo Koo
Filed: 16 Dec 21
Utility
Resistive memory device and methods of making such a resistive memory device
6 Dec 22
An illustrative device disclosed herein includes a bottom electrode, a conformal switching layer positioned above the bottom electrode and a top electrode positioned above the conformal switching layer.
Curtis Chun-I Hsieh, Wanbing Yi, Benfu Lin, Cing Gie Lim, Wei-Hui Hsu, Juan Boon Tan
Filed: 31 Jul 20
Utility
Electronic circuit having serial latch scan chains
28 Oct 19
The invention relates to an electronic circuit (10) having one or more latch scan chains (12), the electronic circuit (10) comprising (i) a built-in test structure (14); (ii) generation means (16) for simultaneously generating scan-in data for each of said scan chains (12); (iii) interception means (18) for simultaneously intercepting test lines (20) of said scan chains (12), said test lines (20) comprising scan-in lines (22) and/or control lines (24).
Tilman Gloekler, Andreas Koenig, Jens Kuenzer, Cedric Lichtenau
Filed: 20 Oct 14
Utility
Method of patterning target layer
28 Oct 19
The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method.
Syed Muhammad Yasser Sherazi, Guillaume Bouche, Julien Ryckaert
Filed: 22 Oct 17
Utility
Integrated circuits having single state memory reference cells and methods for operating the same
28 Oct 19
Integrated circuits including memory cells and methods for operating memory cells are provided.
Yentsai Huang
Filed: 5 Aug 18
Utility
Cap structure
28 Oct 19
The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture.
Jinsheng Gao, Daniel Jaeger, Chih-Chiang Chang, Michael Aquilino, Patrick Carpenter, Junsic Hong, Mitchell Rutkowski, Haigou Huang, Huy Cao
Filed: 28 Jan 18
Utility
Hybrid material electrically programmable fuse and methods of forming
28 Oct 19
Methods of forming a hybrid electrically programmable fuse (e-fuse) structure and the hybrid e-fuse structure are disclosed.
Chun Yu Wong, Jagar Singh
Filed: 24 Aug 17
Utility
Thermally enhanced package to reduce thermal interaction between dies
28 Oct 19
A method of reducing heat flow between IC chips and the resulting device are provided.
Janak Patel, Subramanian Srikanteswara Iyer, Daniel Berger
Filed: 30 Oct 17
Utility
Radio frequency switches with air gap structures
28 Oct 19
The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture.
Anthony K. Stamper, Steven M. Shank, John J. Ellis-Monaghan, Siva P. Adusumilli
Filed: 9 Jul 17
Utility
Epitaxial region for embedded source/drain region having uniform thickness
28 Oct 19
A semiconductor structure including a source/drain region is disclosed.
Yoong Hooi Yong, Yanping Shen, Hsien-Ching Lo, Xusheng Wu, Joo Tat Ong, Wei Hong, Yi Qi, Dongil Choi, Yongjun Shi, Alina Vinslava, James Psillas, Hui Zang
Filed: 13 Nov 17
Utility
Methods, apparatus, and manufacturing system for forming source and drain regions in a vertical field effect transistor
28 Oct 19
A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process.
Ajey Poovannummoottil Jacob, Xuan Anh Tran, Hui Zang, Bala Haran, Suryanarayana Kalaga
Filed: 24 May 18
Utility
Methods of forming vertical field effect transistors with self-aligned contacts and the resulting structures
28 Oct 19
Disclosed are methods wherein vertical field effect transistor(s) (VFET(s)) and isolation region(s) are formed on a substrate.
John H. Zhang, Ruilong Xie, Mahender Kumar
Filed: 30 May 18
Utility
Control of length in gate region during processing of VFET structures
28 Oct 19
Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.
Chanro Park, Steven Bentley, Ruilong Xie, Min Gyu Sung
Filed: 27 Jul 17
Utility
Methods, Apparatus and System for Stringer Defect Reduction In a Trench Cut Region of a Finfet Device
23 Oct 19
At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue.
Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
Filed: 28 Jun 19
Utility
Cap Removal for Gate Electrode Structures with Reduced Complexity
23 Oct 19
The present disclosure relates to manufacturing techniques and respective semiconductor devices in which the capping material of gate electrode structures may be removed together with portions of the capping material of resistors on the basis of a highly controllable directional etch process, wherein raised drain and source regions may be protected on the basis of a fill material.
Hans-Juergen Thees, Peter Baars
Filed: 18 Apr 18
Utility
Methods, Apparatus, and System for Reducing Leakage Current in Semiconductor Devices
23 Oct 19
Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.
Arkadiusz Malinowski, Jagar Singh
Filed: 23 Apr 18
Utility
Heterojunction Bipolar Transistors with an Inverted Crystalline Boundary In the Base Layer
23 Oct 19
Fabrication methods and device structures for a heterojunction bipolar transistor.
Vibhor Jain, Pernell Dongmo, Cameron Luce, James W. Adkisson, Qizhi Liu
Filed: 23 Apr 18
Utility
Wideband Low Noise Amplifier Having DC Loops with Back Gate Biased Transistors
23 Oct 19
Methods form amplifier device structures that include first-third amplifier devices.
Konstantinos Manetakis, Thomas G. McKay
Filed: 22 Apr 18
Utility
Material Combinations for Polish Stops and Gate Caps
23 Oct 19
Structures for a field-effect transistor and methods of forming a structure for field-effect transistor.
Haigou Huang, Jiehui Shu, Chih-Chiang Chang, Xingzhao Shi, Jinsheng Gao, Huy Cao
Filed: 17 Apr 18
Utility
Method, Apparatus, and System for Fin-over-nanosheet Complementary Field-effect-transistor
23 Oct 19
A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type.
Ruilong Xie, Steven Soss, Steven Bentley, Daniel Chanemougame, Julien Frougier, Bipul Paul, Lars Liebmann
Filed: 19 Apr 18