71 patents
Utility
Galvanic isolation using isolation break between redistribution layer electrodes
17 Oct 23
A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode.
Bong Woong Mun, Wanbing Yi, Juan Boon Tan, Jeoung Mo Koo
Filed: 16 Dec 21
Utility
Resistive memory device and methods of making such a resistive memory device
6 Dec 22
An illustrative device disclosed herein includes a bottom electrode, a conformal switching layer positioned above the bottom electrode and a top electrode positioned above the conformal switching layer.
Curtis Chun-I Hsieh, Wanbing Yi, Benfu Lin, Cing Gie Lim, Wei-Hui Hsu, Juan Boon Tan
Filed: 31 Jul 20
Utility
Electronic circuit having serial latch scan chains
28 Oct 19
The invention relates to an electronic circuit (10) having one or more latch scan chains (12), the electronic circuit (10) comprising (i) a built-in test structure (14); (ii) generation means (16) for simultaneously generating scan-in data for each of said scan chains (12); (iii) interception means (18) for simultaneously intercepting test lines (20) of said scan chains (12), said test lines (20) comprising scan-in lines (22) and/or control lines (24).
Tilman Gloekler, Andreas Koenig, Jens Kuenzer, Cedric Lichtenau
Filed: 20 Oct 14
Utility
Method of patterning target layer
28 Oct 19
The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method.
Syed Muhammad Yasser Sherazi, Guillaume Bouche, Julien Ryckaert
Filed: 22 Oct 17
Utility
Hybrid material electrically programmable fuse and methods of forming
28 Oct 19
Methods of forming a hybrid electrically programmable fuse (e-fuse) structure and the hybrid e-fuse structure are disclosed.
Chun Yu Wong, Jagar Singh
Filed: 24 Aug 17
Utility
Thermally enhanced package to reduce thermal interaction between dies
28 Oct 19
A method of reducing heat flow between IC chips and the resulting device are provided.
Janak Patel, Subramanian Srikanteswara Iyer, Daniel Berger
Filed: 30 Oct 17
Utility
Methods, apparatus, and manufacturing system for forming source and drain regions in a vertical field effect transistor
28 Oct 19
A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process.
Ajey Poovannummoottil Jacob, Xuan Anh Tran, Hui Zang, Bala Haran, Suryanarayana Kalaga
Filed: 24 May 18
Utility
Cap structure
28 Oct 19
The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture.
Jinsheng Gao, Daniel Jaeger, Chih-Chiang Chang, Michael Aquilino, Patrick Carpenter, Junsic Hong, Mitchell Rutkowski, Haigou Huang, Huy Cao
Filed: 28 Jan 18
Utility
Radio frequency switches with air gap structures
28 Oct 19
The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture.
Anthony K. Stamper, Steven M. Shank, John J. Ellis-Monaghan, Siva P. Adusumilli
Filed: 9 Jul 17
Utility
Epitaxial region for embedded source/drain region having uniform thickness
28 Oct 19
A semiconductor structure including a source/drain region is disclosed.
Yoong Hooi Yong, Yanping Shen, Hsien-Ching Lo, Xusheng Wu, Joo Tat Ong, Wei Hong, Yi Qi, Dongil Choi, Yongjun Shi, Alina Vinslava, James Psillas, Hui Zang
Filed: 13 Nov 17
Utility
Integrated circuits having single state memory reference cells and methods for operating the same
28 Oct 19
Integrated circuits including memory cells and methods for operating memory cells are provided.
Yentsai Huang
Filed: 5 Aug 18
Utility
Control of length in gate region during processing of VFET structures
28 Oct 19
Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.
Chanro Park, Steven Bentley, Ruilong Xie, Min Gyu Sung
Filed: 27 Jul 17
Utility
Methods of forming vertical field effect transistors with self-aligned contacts and the resulting structures
28 Oct 19
Disclosed are methods wherein vertical field effect transistor(s) (VFET(s)) and isolation region(s) are formed on a substrate.
John H. Zhang, Ruilong Xie, Mahender Kumar
Filed: 30 May 18
Utility
Double barrier layer sets for contacts in semiconductor device
21 Oct 19
Methods of forming a contact for a semiconductor device with double barrier layer sets, and a device so formed are disclosed.
Aditya Kumar, Shiv Kumar Mishra, Jean-Baptiste Jacques Laloƫ, Wen Zhi Gao
Filed: 27 Aug 17
Utility
Stacked elongated nanoshapes of different semiconductor materials and structures that incorporate the nanoshapes
21 Oct 19
Disclosed herein are a method of forming stacked elongated nanoshapes (NSs) (e.g., stacked nanowires (NWs)) of different semiconductor materials above a substrate, a method of forming different devices (e.g., stacked field effect transistors (FETs) having different type conductivities) using the stacked NSs and the resulting structures.
Bartlomiej J. Pawlak, Guillaume Bouche, Ajey P. Jacob
Filed: 21 Jun 17
Utility
Diffused contact extension dopants in a transistor device
21 Oct 19
The present disclosure is directed to various methods of diffusing contact extension dopants in a transistor device and the resulting devices.
Jianwei Peng, Haigou Huang, Qun Gao, Xin Wang
Filed: 27 Jun 18
Utility
Insulating inductor conductors with air gap using energy evaporation material (EEM)
21 Oct 19
A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion.
Sunil K. Singh, Jagar Singh
Filed: 10 Oct 17
Utility
Tone inversion method and structure for selective contact via patterning
21 Oct 19
A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer.
Xiaofeng Qiu, Michael V. Aquilino, Patrick D. Carpenter, Jessica Dechene, Ming Hao Tang, Haigou Huang, Huy Cao
Filed: 13 Feb 17
Utility
Methods of forming replacement gate structures on transistor devices
21 Oct 19
One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening.
Jiehui Shu, Chang Seo Park, Shimpei Yamaguchi, Tao Han, Yong Mo Yang, Jinping Liu, Hyuck Soo Yang
Filed: 29 Oct 17
Utility
Methodology for early detection of TS to PC short issue
21 Oct 19
Methods for enabling in-line detection of TS-PC short defects at the TS-CMP processing stage are provided.
Ming Lei
Filed: 5 Jan 16