71 patents
Page 4 of 4
Utility
Multiple-layer spacers for field-effect transistors
30 Sep 19
Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor.
Tao Han, Zhenyu Hu, Jinping Liu, Hsien-Ching Lo, Jianwei Peng
Filed: 18 Jan 18
Utility
Insulating gate separation structure
30 Sep 19
One illustrative integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, the first and second transistors having a gate width direction and a gate length direction that is substantially normal to the gate width direction, and an insulating gate separation structure positioned between the first and second final gate structures, the insulating gate separation structure comprising an upper portion and a lower portion, the lower portion having a first lateral width in the gate width direction that is substantially uniform throughout a vertical height of the lower portion, the upper portion having a substantially uniform second lateral width in the gate width direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.
Guowei Xu, Hui Zang, Haiting Wang, Yue Zhong
Filed: 17 Sep 18
Utility
Multi-step insulator formation in trenches to avoid seams in insulators
30 Sep 19
Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches.
Asli Sirman, Jiehui Shu, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu
Filed: 26 Mar 18
Utility
Method of forming integrated circuit with gate-all-around field effect transistor and the resulting structure
30 Sep 19
Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure.
Ruilong Xie, Balasubramanian Pranatharthiharan, Pietro Montanini, Julien Frougier
Filed: 9 Jan 18
Utility
Vertical vacuum channel transistor
30 Sep 19
A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
Qing Liu, Ruilong Xie, Chun-chen Yeh
Filed: 31 Aug 17
Utility
Methods, apparatus, and system for frequency doubler using a passive mixer for millimeter wave devices
30 Sep 19
We disclose frequency doublers for use in millimeter-wave devices.
See Taur Lee, Abdellatif Bellaouar
Filed: 21 Mar 18
Utility
Testing phase noise in output signal of device under test using transformable frequency signals
30 Sep 19
Embodiments of the present disclosure provide a system, method, and program product to test phase noise.
Mustapha Slamani, Rebecca R. Percy
Filed: 6 Jun 18
Utility
Feed forward equalizer with power-optimized distributed arithmetic architecture and method
30 Sep 19
A distributed arithmetic feed forward equalizer (DAFFE) and method.
Krishnan S. Rengarajan, Vaibhav A. Ruparelia
Filed: 10 Dec 18
Utility
Linear feedback shift register-based clock signal generator, time domain-interleaved analog to digital converter and methods
30 Sep 19
Disclosed is a linear feedback shift register (LFSR)-based clock signal generator that includes an LFSR, which outputs multi-bit states based on a system clock signal (CLK0).
Steven E. Mikes, Hayden C. Cranford, Jr., John K. Koehler, Steven J. Baumgartner
Filed: 9 Oct 18
Utility
Multiple contact probe head disassembly method and system
30 Sep 19
A system and method for disassembling a multiple contact probe head including a plurality of contact probes positioned by a first die at a first end of the plurality of probes and a second die at a second end of the plurality of probes, are provided.
Marvin G. L. Montaque, Stephen P. Ayotte, David L. Gardell
Filed: 1 Feb 16
Utility
On-chip reliability monitor and method
30 Sep 19
Disclosed are an on-chip reliability monitor and method.
John A. Fifield, Eric Hunt-Schroeder, Mark D. Jacunski
Filed: 22 Feb 18