71 patents
Page 2 of 4
Utility
Sense-line muxing scheme
14 Oct 19
The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.
Igor Arsovski, Qing Li, Xiaoli Hu, Wei Zhao, Jieyao Liu
Filed: 22 Aug 17
Utility
Memory array including distributed reference cells for current sensing
14 Oct 19
An array of memory cells in rows and columns with each column having a corresponding reference cell and a corresponding comparator.
John A. Fifield, Eric Hunt-Schroeder
Filed: 10 Jul 18
Utility
Integrated circuit chip with molding compound handler substrate and method
14 Oct 19
Disclosed are integrated circuit (IC) chip structures (e.g., radio frequency (RF) IC chip structures) and methods of forming the structures with an electrically insulative molding compound handler substrate.
Shahid A. Butt, Christopher L. Tessler
Filed: 20 Dec 16
Utility
Integrated circuit product having a through-substrate-via (TSV) and a metallization layer that are formed after formation of a semiconductor device
14 Oct 19
An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material.
Himani Suhag Kamineni, Vimal Kumar Kamineni, Daniel Smith, Maxwell Lippitt
Filed: 22 Jan 18
Utility
Method for forming replacement gate structures for vertical transistors
14 Oct 19
The present disclosure is directed to various embodiments of a method for forming replacement gate structures for vertical transistors.
Steven Soss, Steven Bentley
Filed: 4 Jul 18
Utility
Device structures for a silicon-on-insulator substrate with a high-resistance handle wafer
14 Oct 19
Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer.
Renata Camillo-Castillo, Hanyi Ding, Natalie B. Feilchenfeld, Vibhor Jain, Anthony K. Stamper
Filed: 21 Jun 15
Utility
Self-aligned multiple patterning processes with layered mandrels
14 Oct 19
Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning.
Jiehui Shu, Xiaohan Wang, Qiang Fang, Zhiguo Sun, Jinping Liu, Hui Zang
Filed: 10 Apr 18
Utility
Hard mask layer to reduce loss of isolation material during dummy gate removal
14 Oct 19
A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures.
Ruilong Xie, Min Gyu Sung, Chanro Park, Hoon Kim
Filed: 30 Oct 16
Utility
Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability
14 Oct 19
The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture.
John M. Safran, Jochonia N. Nxumalo, Joyce C. Liu, Sami Rosenblatt, Chandrasekharan Kothandaraman
Filed: 1 Nov 17
Utility
Sealed cavity structures with a planar surface
14 Oct 19
The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture.
Siva P. Adusumilli, Anthony K. Stamper, Laura J. Schutz, Cameron E. Luce
Filed: 21 Jan 18
Utility
Transistor-based semiconductor device with air-gap spacers and gate contact over active area
14 Oct 19
A semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween.
Ruilong Xie, Min Gyu Sung, Chanro Park, Lars Wolfgang Liebmann, Hoon Kim
Filed: 14 Nov 16
Utility
Gate contact structures and self-aligned contact process
14 Oct 19
The present disclosure relates to semiconductor structures and, more particularly, to gate contact structures and self-aligned contact process and methods of manufacture.
Hui Zang, Ruilong Xie
Filed: 13 Jun 18
Utility
Method and structure for protecting gates during epitaxial growth
14 Oct 19
Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth.
Xiuyu Cai, Ying Hao Hsieh
Filed: 25 Feb 18
Utility
Managing data flow in VCSEL-based optical communications system
14 Oct 19
Methods according to the disclosure include methods for managing data flow in an optical communications system having a plurality of vertical cavity surface emitting lasers (VCSELs).
Hayden C. Cranford, Jr., Jonathan E. Proesel, Rashmi R. Bindu
Filed: 24 Aug 17
Utility
On-demand feed forward equalizer with distributed arithmetic architecture and method
14 Oct 19
Disclosed is a power-optimized distributed arithmetic (DA)-based feed forward equalizer (FFE) that performs on-demand equalization processing of a data sample.
Krishnan S. Rengarajan, Vaibhav A. Ruparelia, Panduga Shiva Shankar Reddy
Filed: 3 Feb 19
Utility
Negative capacitance integration through a gate contact
14 Oct 19
A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area.
Steven Bentley, Rohit Galatage, Puneet Harischandra Suvarna
Filed: 12 Oct 17
Utility
Crystal oscillator and the use thereof in semiconductor fabrication
14 Oct 19
Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes.
Cyril Cabral, Jr., Lawrence A. Clevenger, John M. Cohn, Jeffrey P. Gambino, William J. Murphy, Anthony J. Telensky
Filed: 11 Apr 18
Utility
Local trap-rich isolation
14 Oct 19
A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity.
Steven M. Shank, Michel Abou-Khalil
Filed: 11 Apr 18
Utility
Metal-insulator-metal capacitors with enlarged contact areas
14 Oct 19
Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor.
Sipeng Gu, Jianwei Peng, Xusheng Wu, Yi Qi, Jeffrey Chee
Filed: 15 Jan 18
Utility
Cut inside replacement metal gate trench to mitigate N-P proximity effect
14 Oct 19
The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture.
Balaji Kannan, Ayse M. Ozbek, Tao Chu, Bala Haran, Vishal Chhabra, Katsunori Onishi, Guowei Xu
Filed: 12 Oct 17