71 patents
Page 3 of 4
Utility
Methods, apparatus and system for forming sigma shaped source/drain lattice
14 Oct 19
At least one method, apparatus and system disclosed herein involves forming a sigma shaped source/drain lattice.
Xusheng Wu, Hong Yu
Filed: 11 Sep 17
Utility
Balancing collector contamination of a light source by selective deposition
14 Oct 19
A method includes identifying a first contamination region of a collector of a light source and enabling a subset of a plurality of temperature control elements positioned on the collector to cause a second contamination region to be formed on the collector symmetric to the first contamination region.
Erik R. Hosler, Sheldon J. Meyers
Filed: 9 Jul 18
Utility
Waveguides including a patterned dielectric layer
14 Oct 19
Structures that include a waveguide and methods of fabricating a structure that includes a waveguide.
Yusheng Bian, Abu Thomas, Ajey Poovannummoottil Jacob, Kenneth J. Giewont, Karen Nummy, Andreas Stricker, Bo Peng
Filed: 24 Oct 18
Utility
Auto test grouping/clock sequencing for at-speed test
7 Oct 19
A method includes: defining a plurality of clock architecture attributes for a plurality of clock domains to be tested; assigning each one of the plurality of clock domains to a first test group; and refining the assignment of each one of the plurality of clock domains based on the plurality of clock architecture attributes until each of the plurality of clock domains is grouped into a current test group.
Hardik P. Bhagat, Mark R. Taylor, Baalaji Konda Ramamoorthy, Douglas E. Sprague, Greeshma Jayakumar
Filed: 18 Oct 15
Utility
Waveguide bends with field confinement
7 Oct 19
Structures including waveguide bends, methods of fabricating a structure that includes waveguide bends, and systems that integrate optical components containing different materials.
Yusheng Bian, Ajey Poovannummoottil Jacob
Filed: 17 Jul 18
Utility
Methods, apparatus and system for forming a FinFET device comprising a first portion capable of operating at a first voltage and a second portion capable of operating at a second voltage
7 Oct 19
At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage.
Shahab Siddiqui, Beth Baumert, Abu Naser M. Zainuddin, Luigi Pantisano
Filed: 21 Nov 17
Utility
Interconnect structure having power rail structure and related method
7 Oct 19
Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer.
Erdem Kaltalioglu, Atsushi Ogino
Filed: 9 May 18
Utility
Zero test time memory using background built-in self-test
7 Oct 19
The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.
Igor Arsovski, Eric D. Hunt-Schroeder, Michael A. Ziegerhofer
Filed: 3 Apr 17
Utility
Arc-resistant crackstop
7 Oct 19
The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture.
Vincent J. McGahay, Nicholas A. Polomoff, Shaoning Yao, Anupam Arora
Filed: 6 Sep 17
Utility
Fins with single diffusion break facet improvement using epitaxial insulator
7 Oct 19
The present disclosure relates to semiconductor structures and, more particularly, to fin structures with single diffusion break facet improvement using an epitaxial insulator and methods of manufacture.
Chun Yu Wong, Hui Zang, Xusheng Wu
Filed: 16 Oct 17
Utility
Dual port vertical transistor memory cell
7 Oct 19
A first S/D region includes a first P-type region, a first N-type region, and a first conductive layer thereon to define a first cell node.
Randy W. Mann, Bipul C. Paul
Filed: 28 May 18
Utility
Cascode heterojunction bipolar transistor
7 Oct 19
Fabrication methods and device structures for heterojunction bipolar transistors.
Vibhor Jain, Alvin J. Joseph, Qizhi Liu
Filed: 24 Apr 19
Utility
Shielded MRAM cell
7 Oct 19
One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode.
Dimitri Houssameddine, Chenchen Jacob Wang, Bin Liu, Soh Yun Siah
Filed: 17 Jan 18
Utility
Chip-to-chip and chip-to-substrate interconnections in multi-chip semiconductor devices
7 Oct 19
A multi-chip semiconductor device with multi-level structure including a substrate with a top substrate surface, a cavity with a depth in the substrate, a first chip having a top first chip surface with a first chip height, optionally including a second chip having a top second chip surface with a second chip height, and a connecting passive chip bridging the first chip, the second chip and the substrate by solder bumps wherein the solder bumps enable the connecting passive chip to be level.
Mukta Farooq, Koushik Ramachandran, Eric Perfecto, Ian Melville
Filed: 29 May 18
Utility
Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods
7 Oct 19
Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting.
Hui Zang, Min-hwa Chi
Filed: 31 May 18
Utility
Integration of vertical-transport transistors and electrical fuses
7 Oct 19
Structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit.
Ruilong Xie, Kangguo Cheng, Tenko Yamashita, Chun-chen Yeh
Filed: 30 Oct 16
Utility
Injection locked oscillator system and processes
7 Oct 19
The present disclosure relates to an injection locked oscillator system and processes and, more particularly, to structures and processes for generating an inductor-less frequency multiplier using injection locking and histogram calibration with a back-gate process.
Stephen Allott, Julian Jenkins
Filed: 1 Nov 17
Utility
Event based integrated driver system and light emitting diode (LED) driver system
7 Oct 19
An event based integrated driver system for an end-use power based application is disclosed.
Hrishikesh Bhagwat, Krishnadas Bhagwat, Rajesh Swaminathan, Somnath Samantha, Abhisek Khare
Filed: 12 Jun 14
Utility
Waveguide-to-waveguide couplers with multiple tapers
30 Sep 19
Waveguide-to-waveguide couplers, systems that include waveguide-to-waveguide couplers, and methods of fabricating waveguide-to-waveguide couplers.
Yusheng Bian, Ajey Poovannummoottil Jacob, Steven M. Shank
Filed: 1 May 18
Utility
Polarization splitters based on stacked waveguides
30 Sep 19
Structures for a polarization splitter and methods of forming a polarization splitter.
Abu Thomas, Yusheng Bian, Ajey Poovannummoottil Jacob
Filed: 12 Nov 18