61 patents
Page 3 of 4
Utility
Characterization vehicles for printed circuit board and system design
19 Jan 21
A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board.
Brian E. Stine
Filed: 17 Dec 19
Utility
Maintenance Scheduling for Semiconductor Manufacturing Equipment
9 Dec 20
A maintenance tool for semiconductor process equipment and components.
Tomonori Honda, Jeffrey Drue David, Lin Lee Cheong
Filed: 24 Aug 20
Utility
Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies
30 Nov 20
Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.
Sharad Saxena, Tomasz Brozek, Yuan Yu, Mike Kyu Hyon Pak, Meindert Martin Lunenborg
Filed: 31 May 17
Utility
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas
30 Nov 20
A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas.
Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
Filed: 30 Mar 18
Utility
Snap-to valid pattern system and method
12 Oct 20
Described is a method for implementing a snap to capability that enables the manufactured of a valid pattern in a semiconductor device, based upon an originally invalid pattern.
Elizabeth Lagnese, Jonathan Haigh
Filed: 4 Sep 17
Utility
Selective inclusion/exclusion of semiconductor chips in accelerated failure tests
14 Sep 20
Testing data is evaluated by machine learning tools to determine whether to include or exclude chips from further testing.
Lin Lee Cheong, Tomonori Honda, Rohan D. Kekatpure, Lakshmikar Kuravi, Jeffrey Drue David
Filed: 25 Mar 19
Utility
IC with test structures embedded within a contiguous standard cell area
14 Sep 20
An IC includes a contiguous standard cell area with first, second, and third TS-GATE-short-configured test area geometries disposed therein.
Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
Filed: 28 Sep 18
Utility
Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structure
7 Sep 20
Described here is an apparatus and method of testing a vertical (3D) semiconductor memory structure coupled between word lines and bit lines, by means of a direct connections of a plurality of test pads to word lines and bit lines of the memory structure on memory product wafer.
Tomasz Brozek
Filed: 3 Jun 18
Utility
Process control techniques for semiconductor manufacturing processes
3 Aug 20
Techniques for measuring and/or compensating for process variations in a semiconductor manufacturing processes.
Jeffrey Drue David
Filed: 24 Nov 15
Utility
Direct memory characterization using periphery transistors
8 Jun 20
Disclosed is a system and method for performing direct memory characterization of memory cells in a memory array using peripheral transistors.
Dong Kyu Lee, Kelvin Yih-Yuh Doong, Tuan Pham, Klaus Schuegraf, Christoph Dolainsky, Huan Tsung Huang, Hendrik Schneider
Filed: 5 Dec 18
Utility
Failure detection for wire bonding in semiconductors
18 May 20
Disclosed is a system and method for collecting trace data of integrated circuits from the back-end assembly tools and using yield, reliability, and burn-in data to distinguish good circuit traces from bad ones.
Brian Stine, Richard Burch, Nobuchika Akiya
Filed: 20 Sep 18
Utility
Passive array test structure for cross-point memory characterization
4 May 20
An apparatus and method for testing two-terminal memory elements organized as a cross-point memory array.
Tomasz Brozek, Christopher Hess, Rakesh Vallishayee, Meindert Lunenborg, Hendrik Schneider, Yuan Yu, Amit Joag, SiewHoon Ng
Filed: 10 Jul 18
Utility
Method for applying charge-based-capacitance-measurement with switches using only NMOS or only PMOS transistors
4 May 20
Described is a CBCM technique that works only with PMOS transistors or only with NMOS transistors.
Sharad Saxena
Filed: 18 Sep 16
Utility
Characterization Vehicles for Printed Circuit Board and System Design
15 Apr 20
A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board.
Brian E. Stine
Filed: 16 Dec 19
Utility
IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same
13 Apr 20
The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.
Jonathan Haigh, Elizabeth Lagnese
Filed: 6 Jul 17
Utility
Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells
16 Mar 20
Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes.
Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
Filed: 3 Apr 16
Utility
Standard cell design conformance using boolean assertions
17 Feb 20
Disclosed techniques conform standard cells in an integrated circuit design into a valid template pattern using a template-based approach to standard cell design.
Elizabeth Lagnese
Filed: 29 Nov 18
Utility
Method for manufacturing a semiconductor product wafer
27 Jan 20
Improved methods for manufacturing semiconductor product wafer with the additional use of non-product masks are described.
Yih-Yuh Kelvin Doong, Sheng-Che Lin
Filed: 17 Dec 17
Utility
Test structures and method for electrical measurement of FinFET fin height
6 Jan 20
Methods of measuring fin height electrically for devices fabricated using FinFET technology are disclosed here.
Sharad Saxena, Jianjun Cheng, Yuan Yu
Filed: 18 Sep 16
Utility
Characterization vehicles for printed circuit board and system design
23 Dec 19
A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board.
Brian E Stine
Filed: 15 Oct 18