65 patents
Utility
Network switching with co-resident data-plane and network interface controllers
22 Nov 22
A system with co-resident data-plane and network interface controllers embodying a method for network switching of a data packet incoming from a network at a packet input processor portion of a network interface resource comprising the packet input processor, a packet output processor, and a network interface controller, implemented on a chip, to a target entity, is disclosed.
Wilson Parkhurst Snyder, II, Muhammad Raghib Hussain
Filed: 16 Sep 18
Utility
Low latency inter-chip communication mechanism in multi-chip processing system
14 Sep 21
Systems and methods of multi-chip processing with low latency and congestion.
Craig Barner, David Asher, Richard Kessler, Bradley Dobbie, Daniel Dever, Thomas F. Hummel, Isam Akkawi
Filed: 31 Jan 19
Utility
Method of using bit vectors to allow expansion and collapse of header layers within packets for enabling flexible modifications and an apparatus thereof
29 Jun 21
Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification.
Chirinjeev Singh, Tsahi Daniel, Gerald Schmidt
Filed: 13 Mar 17
Utility
Prefetching data to reduce cache misses
13 Apr 21
A first memory request including a first virtual address is received.
David Carlson, Shubhendu S. Mukherjee
Filed: 26 Nov 18
Utility
Hierarchical statistically multiplexed counters and a method thereof
16 Nov 20
Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude.
Weihuang Wang, Gerald Schmidt, Srinath Atluri, Weinan Ma, Shrikant Sundaram Lnu
Filed: 26 Jun 18
Utility
Systems and methods for vectorized FFT for multi-dimensional convolution operations
5 Oct 20
A new approach is proposed to support efficient convolution for deep learning by vectorizing multi-dimensional input data for multi-dimensional fast Fourier transform (FFT) and direct memory access (DMA) for data transfer.
Mehran Nekuii
Filed: 10 May 17
Utility
Protocol independent programmable switch (PIPS) for software defined data center networks
21 Sep 20
A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports.
Guy Townsend Hutchison, Sachin Ramesh Gandhi, Tsahi Daniel, Gerald Schmidt, Albert Fishman, Martin Leslie White, Zubin Shah
Filed: 17 Oct 17
Utility
Method and system for reconfigurable parallel lookups using multiple shared memories
21 Sep 20
Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks.
Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
Filed: 15 Mar 18
Utility
Apparatus and method of generating lookups and making decisions for packet modifying and forwarding in a software-defined network engine
17 Aug 20
Embodiments of the present invention relate to a Lookup and Decision Engine (LDE) for generating lookup keys for input tokens and modifying the input tokens based on contents of lookup results.
Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Harish Krishnamoorthy
Filed: 28 May 18
Utility
Low Latency Inter-chip Communication Mechanism In Multi-chip Processing System
5 Aug 20
Systems and methods of multi-chip processing with low latency and congestion.
Craig Barner, David Asher, Richard Kessler, Brad Dobbie, Daniel Dever, Tom Hummel, Isam Akkawi
Filed: 30 Jan 19
Utility
Pair Merge Execution Units for Microinstructions
5 Aug 20
An instruction execution circuit operable to reduce two or more micro-operations into one by producing multiple permutation and merge results in one execution cycle.
David Kravitz, David A. Carlson
Filed: 30 Jan 19
Utility
Method and apparatus for analytics in a network switch
8 Jun 20
Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling.
Weihuang Wang, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
Filed: 27 May 14
Utility
Prefetching Data to Reduce Cache Misses
27 May 20
A first memory request including a first virtual address is received.
David CARLSON, Shubhendu S. MUKHERJEE
Filed: 25 Nov 18
Utility
Apparatus and a method of detecting errors on registers
18 May 20
An error detection circuit on a semiconductor chip detects whether soft errors have affected flip-flop implemented registers on the semiconductor chip.
Vishal Anand, Harish Krishnamoorthy, Guy Hutchison
Filed: 21 Oct 14
Utility
Methods and systems for generating interrupts by a response direct memory access module
20 Apr 20
Methods and systems for generating interrupts are provided.
Dharma Konda, Ben Hui
Filed: 17 Jan 18
Utility
Packet processing system, method and device having reduced static power consumption
6 Apr 20
A buffer logic unit of a packet processing device including a power gate controller.
Enrique Musoll
Filed: 29 Mar 15
Utility
Method of handling large protocol layers for configurable extraction of layer information and an apparatus thereof
6 Apr 20
Embodiments of the apparatus for handling large protocol layers relate to an implementation that optimizes a field selection circuit.
Vishal Anand, Tsahi Daniel, Premshanth Theivendran
Filed: 18 Jun 14
Utility
Method and Apparatus for Providing a Low Latency Transmission System Using Adjustable Buffers
1 Apr 20
One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“A/V”) data with enhanced quality of service (“QoS”).
Francisco J. Roncero Izquierdo, Gorka Garcia
Filed: 28 Nov 19
Utility
Phantom Queue Link Level Load Balancing System, Method and Device
18 Mar 20
A data processing system includes a phantom queue for each of a plurality of output ports each associated with an output link for outputting data.
Martin Leslie White
Filed: 24 Nov 19
Utility
Low latency interconnect protocol for coherent multi-chip communication
16 Mar 20
In one embodiment, a data message is generated at a first system-on-chip (SOC) for transmission to a second SOC.
Steven C. Barner
Filed: 11 Sep 18