65 patents
Page 3 of 4
Utility
Serializer/Deserializer (SerDes) Lanes with Lane-by-Lane Datarate Independence
1 Jan 20
A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane.
Scott E. Meninger
Filed: 11 Sep 19
Utility
Methods and Apparatus for Twiddle Factor Generation for Use with A Programmable Mixed-Radix DFT/IDFT Processor
1 Jan 20
Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values.
Yuanbin Guo, Hong Jik Kim
Filed: 8 Jul 19
Utility
Methods and Apparatus for Control Channel Detection in An Uplink Shared Channel
1 Jan 20
Methods and apparatus for channel detection in an uplink shared control channel.
Yuanbin Guo
Filed: 14 Sep 19
Utility
Phantom queue link level load balancing system, method and device
30 Dec 19
A data processing system includes a phantom queue for each of a plurality of output ports each associated with an output link for outputting data.
Martin Leslie White
Filed: 9 Sep 18
Utility
Combined Conditional Branch and Indirect Branch Target Predictor
18 Dec 19
An example embodiment combines use of a branch predictor with cache-like storage of previously executed branch targets to improve processor performance while minimizing hardware cost.
Edward J. McLellan, David A. Carlson, Rohit P. Thakar
Filed: 14 Jun 18
Utility
Methods and Apparatus for Adaptive Power Profiling in A Baseband Processing System
4 Dec 19
Methods and apparatus for adaptive power profiling in a baseband processing system.
Kalyana S. Venkataraman, Gregg A. Bouchard, Eric Marenger, Ahmed Shahid
Filed: 19 Aug 19
Utility
Methods and apparatus for a unified baseband architecture
2 Dec 19
Methods and apparatus for a unified baseband architecture.
Tejas M. Bhatt, Gregg A. Bouchard, Hong Jik Kim, Jason D. Zebchuk, Ahmed Shahid
Filed: 1 Jun 17
Utility
Write and read common leveling for 4-bit wide drams
2 Dec 19
System and method of read deskew training for ×4 mode memory control interface configurations.
David Da Wei Lin
Filed: 18 Jul 18
Utility
Method and apparatus for using multiple linked memory lists
18 Nov 19
An apparatus and method for queuing data to a memory buffer.
Vamsi Panchagnula, Saurin Patel, Keqin Han, Tsahi Daniel
Filed: 30 Mar 15
Utility
Methods and Apparatus for Symbol-to-Symbol Multiplexing of Control, Data, and Reference Signals on A 5G Uplink
6 Nov 19
Methods and apparatus for symbol-to-symbol multiplexing of control, data, and reference signals on a 5G uplink.
Yuanbin Guo, Hong Jik Kim
Filed: 30 Apr 19
Utility
Methods and Apparatus for Sub-block Based Architecture of Cholesky Decomposition and Channel Whitening
6 Nov 19
Methods and apparatus for sub-block based architecture of Cholesky decomposition and channel whitening.
Yuanbin Guo, Hong Jik Kim
Filed: 28 Dec 18
Utility
Methods and Apparatus for Providing A Demapping System to Demap Uplink Transmissions
6 Nov 19
Methods and apparatus for providing a demapping system to demap uplink transmissions.
Sabih Guzelgoz, Hong Jik Kim
Filed: 5 May 19
Utility
Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing
4 Nov 19
Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing.
Sabih Guzelgoz, Hong Jik Kim, Tejas Maheshbhai Bhatt, Fariba Heidari
Filed: 13 Dec 16
Utility
Compiler architecture for programmable application specific integrated circuit based network devices
4 Nov 19
A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs.
Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
Filed: 5 Nov 17
Utility
Engine architecture for processing finite automata
4 Nov 19
An engine architecture for processing finite automata includes a hyper non-deterministic automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing.
Rajan Goyal, Satyanarayana Lakshmipathi Billa, Yossef Shanava, Gregg A. Bouchard, Timothy Toshio Nakada
Filed: 12 Sep 17
Utility
Methods and Apparatus for Dynamic Acknowledgement List Selection In Detection of Uplink Control Channel Formats
30 Oct 19
Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats.
Yuanbin Guo
Filed: 30 Sep 18
Utility
Methods and Apparatus for Two-stage Ack/dtx Detection
30 Oct 19
Methods and apparatus for two-stage ACK/DTX detection.
Yuanbin Guo, Hong Jik Kim
Filed: 14 Apr 19
Utility
Method and apparatus for port access management at a distributed job manager in a digital multi-processor system
28 Oct 19
A method and a system for port access management at a distributed job manager, encompassing: initializing a port access process for each of one or more ports on a processing device; determining first whether a job is assigned to an active slot identified by an active_slot_id on the processing device, and when the determining is positive: determining second whether the job has been serviced by a port identified by the active_slot_id; and when either the first determining is negative or the second determining is positive then: retesting the first and second determining; else: determining whether the job requires an access to the port identified by the active_slot_id; and when the determining is positive: fetching the port's configuration words; processing the fetched port's configuration words; marking the job as serviced by the port upon conclusion or the processing of the fetched port's configuration words; and recalculating the value of the active_slot_id.
Kalyana Sundaram Venkataraman, Tejas Maheshbhai Bhatt, Hong Jik Kim, Eric Marenger, Ahmed Shahid, Jason Daniel Zebchuk
Filed: 4 May 17
Utility
Scope in decision trees
28 Oct 19
A root node of a decision tree data structure may cover all values of a search space used for packet classification.
Rajan Goyal, Kenneth A. Bullis
Filed: 25 Oct 15
Utility
Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence
28 Oct 19
A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane.
Scott E. Meninger
Filed: 12 Mar 19