41 patents
Page 2 of 3
Utility
Method and apparatus for bypass routing of multicast data packets and avoiding replication to reduce overall switch latency
17 Feb 20
An apparatus for routing multicast data packets, the apparatus includes an ingress port to receive data streams of multicast data packets and status data about egress ports available to transmit the multicast traffic data streams.
Vamsi Panchagnula, Saurin Patel, Keqin Han
Filed: 26 Mar 15
Utility
Method of dynamically renumbering ports and an apparatus thereof
10 Feb 20
Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip.
Vishal Anand, Vamsi Panchagnula
Filed: 17 Jul 17
Utility
Methods and systems for distributing memory requests
10 Feb 20
A memory request, including an address, is accessed.
Richard E. Kessler, David Asher, Shubhendu S. Mukherjee, Wilson P. Snyder, II, David Carlson, Jason Zebchuk, Isam Akkawi
Filed: 10 Sep 18
Utility
Managing memory access requests with prefetch for streams
10 Feb 20
Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.
Shubhendu Sekhar Mukherjee, David Albert Carlson, Srilatha Manne
Filed: 17 Jun 18
Utility
Methods and apparatus for frequency offset estimation
3 Feb 20
Methods and apparatus for frequency offset estimation are disclosed.
Hyun Soo Cheon, Hong Jik Kim, Tejas M. Bhatt
Filed: 30 Dec 18
Utility
Method and apparatus for providing a low latency transmission system using adjustable buffers
6 Jan 20
One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“A/V”) data with enhanced quality of service (“QoS”).
Francisco J. Roncero Izquierdo, Gorka Garcia Rodriguez
Filed: 26 Aug 15
Utility
Phantom queue link level load balancing system, method and device
30 Dec 19
A data processing system includes a phantom queue for each of a plurality of output ports each associated with an output link for outputting data.
Martin Leslie White
Filed: 9 Sep 18
Utility
Methods and apparatus for a unified baseband architecture
2 Dec 19
Methods and apparatus for a unified baseband architecture.
Tejas M. Bhatt, Gregg A. Bouchard, Hong Jik Kim, Jason D. Zebchuk, Ahmed Shahid
Filed: 1 Jun 17
Utility
Write and read common leveling for 4-bit wide drams
2 Dec 19
System and method of read deskew training for ×4 mode memory control interface configurations.
David Da Wei Lin
Filed: 18 Jul 18
Utility
Method and apparatus for using multiple linked memory lists
18 Nov 19
An apparatus and method for queuing data to a memory buffer.
Vamsi Panchagnula, Saurin Patel, Keqin Han, Tsahi Daniel
Filed: 30 Mar 15
Utility
Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing
4 Nov 19
Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing.
Sabih Guzelgoz, Hong Jik Kim, Tejas Maheshbhai Bhatt, Fariba Heidari
Filed: 13 Dec 16
Utility
Compiler architecture for programmable application specific integrated circuit based network devices
4 Nov 19
A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs.
Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
Filed: 5 Nov 17
Utility
Engine architecture for processing finite automata
4 Nov 19
An engine architecture for processing finite automata includes a hyper non-deterministic automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing.
Rajan Goyal, Satyanarayana Lakshmipathi Billa, Yossef Shanava, Gregg A. Bouchard, Timothy Toshio Nakada
Filed: 12 Sep 17
Utility
Method and apparatus for port access management at a distributed job manager in a digital multi-processor system
28 Oct 19
A method and a system for port access management at a distributed job manager, encompassing: initializing a port access process for each of one or more ports on a processing device; determining first whether a job is assigned to an active slot identified by an active_slot_id on the processing device, and when the determining is positive: determining second whether the job has been serviced by a port identified by the active_slot_id; and when either the first determining is negative or the second determining is positive then: retesting the first and second determining; else: determining whether the job requires an access to the port identified by the active_slot_id; and when the determining is positive: fetching the port's configuration words; processing the fetched port's configuration words; marking the job as serviced by the port upon conclusion or the processing of the fetched port's configuration words; and recalculating the value of the active_slot_id.
Kalyana Sundaram Venkataraman, Tejas Maheshbhai Bhatt, Hong Jik Kim, Eric Marenger, Ahmed Shahid, Jason Daniel Zebchuk
Filed: 4 May 17
Utility
Scope in decision trees
28 Oct 19
A root node of a decision tree data structure may cover all values of a search space used for packet classification.
Rajan Goyal, Kenneth A. Bullis
Filed: 25 Oct 15
Utility
Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence
28 Oct 19
A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane.
Scott E. Meninger
Filed: 12 Mar 19
Utility
Methods and apparatus for control channel detection in an uplink shared channel
14 Oct 19
Methods and apparatus for channel detection in an uplink shared control channel.
Yuanbin Guo
Filed: 27 Sep 17
Utility
Packet scheduling using hierarchical scheduling process with priority propagation
14 Oct 19
System and method of data routing according to a hierarchical scheduling process.
Tsahi Daniel, Vamsi Panchagnula
Filed: 13 Nov 14
Utility
Managing lock and unlock operations using traffic prioritization
14 Oct 19
Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread.
Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
Filed: 30 May 17
Utility
Packet parsing engine
14 Oct 19
A packet parsing engine comprises a DMEM configured to store packet data; one or more registers configured to store parsing instructions or parse results; and one or more arithmetic logic units configured to parse the packet data based on the parsing instructions and to derive the parse results.
Wilson Parkhurst Snyder, II, Daniel Adam Katz, Varada Ramesh Ogale
Filed: 7 Jan 14