80 patents
Page 2 of 4
Utility
Information tamper-resistant system and method
27 Dec 22
The present disclosure provides an information tamper-resistant system and method.
Xiong Zhang, Gang Shi
Filed: 12 May 20
Utility
Self-cooling Semiconductor Resistor and Manufacturing Method Thereof
15 Dec 22
Self-cooling semiconductor resistor and manufacturing method thereof are provided.
Xiong ZHANG
Filed: 9 Jun 22
Utility
On-chip Peltier Cooling Device and Manufacturing Method Thereof
15 Dec 22
On-chip peltier cooling devices and manufacturing methods thereof are provided.
Xiong ZHANG
Filed: 9 Jun 22
Utility
Integrated Cooling Device Based on Peltier Effect and Manufacturing Method Thereof
15 Dec 22
Integrated cooling device based on Peltier effect and manufacturing method thereof are provided.
Xiong ZHANG
Filed: 9 Jun 22
Utility
SST Driving Circuit, Chip and Driving Output Method
24 Nov 22
The present disclosure provides an SST driving circuit, a chip, and a driving output method.
Chunlai SUN, Juan DU
Filed: 26 Aug 21
Utility
Apparatus and method for controlling access to memory module
1 Nov 22
An apparatus controls access to a memory module coupled to a host controller via a data bus to exchange data with the host controller.
Yi Li, Gang Shan, Howard Chonghe Yang
Filed: 13 Apr 20
Utility
Power Clamp Circuit, Chip and Dual-clamp Method
27 Oct 22
The present disclosure provides a power clamp circuit, a chip, and a dual-clamp method.
Chunlai SUN
Filed: 27 Aug 21
Utility
Device and Method for Picking Up Top K Values
20 Oct 22
The application discloses a device and a method for picking up top k values from N values.
Jie DAI, Chunyi LI, Zhijie LIU, Zhongyuan CHANG
Filed: 31 Mar 22
Utility
Method and Apparatus for Querying Similar Vectors In a Candidate Vector Set
13 Oct 22
A method for querying in a candidate vector set candidate vectors similar to object vectors is disclosed, wherein the candidate vector set comprises a plurality of candidate vectors each being quantized as having a central vector portion and a residual vector portion, and the candidate vector set comprises a plurality of candidate vector subsets, the method comprising: acquiring a set of object vectors; querying, for each object vector of the set of object vectors, a first number of candidate vector subsets that are closest to the object vector; generating and storing a plurality of common calculation results based on a set of central vector portions and a set of residual vector portions of candidate vectors of the first number of candidate vector subsets; generating and storing pre-calculation results based on the set of object vectors and the set of residual vector portion; and determining, for each object vector of the set of object vectors, a second number of candidate vectors that are similar to the object vector among the candidate vectors in the corresponding first number of candidate vector subsets based on the stored pre-calculation results and common calculation results.
Song XU, Lanxin ZHANG, Yufeng QU, Chunyi LI
Filed: 12 Apr 22
Utility
Information Tamper-resistant System and Method
6 Oct 22
The present disclosure provides an information tamper-resistant system and method.
Xiong ZHANG, Gang SHI
Filed: 12 May 20
Utility
Processing devices and distributed processing systems
27 Sep 22
The present application pertains to a processing device or a distributed processing system using the processing device.
Gang Shan, Ye Yang, Jingzhong Yang
Filed: 21 Dec 20
Utility
Package Substrate Structure and Method for Manufacturing Same
22 Sep 22
The present disclosure provides a package substrate structure and a method for manufacturing the same.
Meng MEI, Gang SHI, Peichun WANG, Guangfeng LI
Filed: 26 Aug 21
Utility
Memory Device with Split Power Supply Capability
15 Sep 22
A memory device includes a printed circuit board having a plurality of conductive layers; memory chips mounted over the printed circuit board, wherein the memory chips comprise at least a first number of memory chips and a second number of memory chips; a first power module mounted over the printed circuit board and for providing a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and a second power module mounted over the printed circuit board and for providing a second set of power supplies to the second number of memory chips through the plurality of conductive layers.
Christopher Cox
Filed: 15 Mar 21
Utility
Apparatus and method for repairing a defect of a memory module, and a memory system
16 Aug 22
The present application discloses an apparatus for repairing a defect of a memory module, comprises: a central buffer having an address recording module for recording defective address information indicating one or more defective memory addresses in the memory module; the central buffer is configured to receive an access command for accessing a target address in the memory module from a memory interface, and to determine whether to generate a repair access command for repairing the target address according to a comparison result; and a data buffer having a data recording module for recording repair data; wherein the data buffer is coupled between the memory interface and the memory module to buffer data interacted therebetween, and is coupled to the central buffer to receive the access command or the repair access command; the data buffer is configured to write target data associated with the access command into the data recording module as repair data corresponding to a target address according to the repair access command, or read repair data from the data recording module as target data corresponding to a target address.
Gang Shan, Yong Zhang
Filed: 28 Jun 20
Utility
Method for testing electrical performance of packaged chip
19 Jul 22
A method for manufacturing an electrical performance test structure of packaged chip, and a method for testing electrical performance of packaged chip, including: providing a first wafer and a second wafer, forming a top metal layer on the first wafer and the second wafer respectively, forming bumps on part of the top metal layer of the first wafer and on part of the top metal layer of the second wafer respectively, removing the top metal layer that is not directly beneath the bumps in the first wafer, and completely retaining the top metal layer in the second wafer, and packaging the first wafer to a first die and packaging the second wafer to a second die, wherein the second die is used as a test structure, and the electrical performance of the second die is used as a reference for electrical performance of the first die.
Meng Mei, Gang Shi, Peichun Wang, Guangfeng Li
Filed: 15 May 20
Utility
Clock driver and memory device comprising the same
5 Jul 22
A clock driver comprises: a clock detector for receiving a plurality pairs of input clock signals of a predetermined clocking protocol, and for generating a protocol identifier indicative of the predetermined clocking protocol; a phase locking loop (PLL) module coupled to receive at least one pair of the plurality pairs of input clock signals, and for generating at least one pair of reference clock signals according to the received at least one pair of input clock signal; and a plurality of multiplexers coupled to the clock detector and to the PLL module.
Yibo Jiang, Leechung Yiu, Christopher Cox, Lizhi Jin
Filed: 25 Sep 21
Utility
Memory controller and method for monitoring accesses to a memory module
14 Jun 22
The application discloses a memory controller coupled between a memory module and a host controller to control accesses of the host controller to the memory module.
Stephen Tai, Yi Li
Filed: 30 Nov 20
Utility
Method and Device for Compressing Neural Network
26 May 22
A method for compressing a neural network includes: obtaining a neural network including J operation layers; compressing a jth operation layer with Kj compression ratios to generate Kj operation branches; obtaining Kj weighting factors; replacing the jth operation layer with the Kj operation branches weighted by the Kj weighting factors to generate a replacement neural network; performing forward propagation to the replacement neural network, a weighted sum operation being performed on Kj operation results generated by the Kj operation branches with the Kj weighting factors and a result of the weighted sum operation being used as an output of the jth operation layer; performing backward propagation to the replacement neural network, updated values of the Kj weighting factors being calculated based on a model loss; and determining an operation branch corresponding to the maximum value of the updated values of the Kj weighting factors as a compressed jth operation layer.
Zhen DONG, Yuanfei NIE, Huan FENG
Filed: 19 Nov 21
Utility
Method and Device for Compressing Neural Network
26 May 22
A method for compressing a neural network includes: obtaining a neural network including a plurality of parameters to be compressed; dividing the parameters into J blocks; compressing a jth block with Kj compression ratios to generate Kj operation branches; obtaining Kj weighting factors; replacing the jth block with the Kj operation branches weighted by the Kj weighting factors to generate a replacement neural network; performing forward propagation to the replacement neural network, a weighted sum operation being performed on Kj operation results generated by the Kj operation branches with the Kj weighting factors and a result of the operation being used as an output; performing backward propagation to the replacement neural network, updated values of the Kj weighting factors being calculated based on a model loss; and determining an operation branch corresponding to the maximum value of the updated values of the Kj weighting factors as a compressed jth block.
Zhen DONG, Yuanfei NIE, Huan FENG
Filed: 22 Nov 21
Utility
Method for Testing Electrical Performance of Packaged Chip
12 May 22
The application discloses a method for manufacturing an electrical performance test structure of packaged chip, and a method for testing electrical performance of packaged chip, including: providing a first wafer and a second wafer, forming a top metal layer on the first wafer and the second wafer respectively, forming bumps on part of the top metal layer of the first wafer and on part of the top metal layer of the second wafer respectively, removing the top metal layer that is not directly beneath the bumps in the first wafer, and completely retaining the top metal layer in the second wafer, and packaging the first wafer to a first die and packaging the second wafer to a second die, wherein the second die is used as a test structure, and the electrical performance of the second die is used as a reference for electrical performance of the first die.
Meng MEI, Gang SHI, Peichun WANG, Guangfeng LI
Filed: 15 May 20