80 patents
Page 3 of 4
Utility
Package Substrate and Manufacturing Method Thereof
5 May 22
A package substrate and a manufacturing method thereof, the method including: forming a package substrate by a first dielectric layer formed by weaving at least fiberglass of a first width and a second dielectric layer formed by weaving at least fiberglass of a second width.
Meng MEI, Gang SHI, Peichun WANG, Guangfeng LI
Filed: 15 May 20
Utility
Computing System and Method for Sharing Device Memories of Different Computing Devices
21 Apr 22
A computing system includes a host computing device and a slave computing device.
Ye YANG, Jingzhong YANG, Gang SHAN
Filed: 26 Aug 21
Utility
Laminate structure and test method for detecting inter-metal dielectric layer defects
8 Mar 22
The present application disclosed a conducting layer-dielectric layer-conducting layer (CDC) laminate structure and test method for detecting defects of an inter-metal dielectric layer.
Xiong Zhang, Chunlai Sun, Peichun Wang, Gang Shi
Filed: 27 May 19
Utility
Asymmetrical I/o Structure
24 Feb 22
An asymmetrical I/O structure is provided.
Xiong ZHANG, Chunlai SUN, Juan DU, Gang SHI, Chonghe YANG
Filed: 19 Aug 21
Utility
Test device and method with built-in self-test logic
22 Feb 22
A test device and method with built-in self-test logic and a communication device.
Dan Wang, Ranran Fan, Xiao Zhu, Zhongyuan Chang, Xin Liu
Filed: 15 Sep 20
Utility
Apparatus and method for testing a defect of a memory module and a memory system
22 Feb 22
The present application discloses an apparatus for testing defects of a memory module comprises a central buffer for generating a test write command and a test read command to indicate testing to a target address in a memory module; and a data buffer coupled to the central buffer to receive the test write command and the test read command; the data buffer is configured to, in response to the test write command, use target data as repair data corresponding to the target address, and write the target data into the memory module; and, in response to the test read command, to read target data from the target address and compare the target data with the repair data, and to send to the central buffer a comparison result of the target data and the repair data; the central buffer is further configured to record the target address as a tested address when generating the test write command, and determine whether to add the tested address to defective address information based on the comparison result associated with the tested address, defective address information is to indicate one or more defective memory addresses in the memory module.
Gang Shan, Yong Zhang
Filed: 2 Jul 20
Utility
Memory controller and method for accessing memory module
18 Jan 22
A memory controller and a method for accessing a memory module are provided.
Gang Shan, Howard Chonghe Yang, Yi Li
Filed: 11 Apr 18
Utility
Memory Controller and a Method for Controlling Access to a Memory Module
25 Nov 21
The application discloses a memory controller coupled between a memory module and a host controller to control access of the host controller to the memory module, comprising a central buffer coupled between the host controller and the memory module.
Yi LI, Gang SHAN, Guohui LI, Chunhui ZHANG
Filed: 21 May 21
Utility
Memory controller
26 Oct 21
The application discloses a memory controller coupled to a memory module for controlling access to the memory module.
Howard Chonghe Yang, Zhongyuan Chang, Chunyi Li
Filed: 20 Dec 19
Utility
Apparatus and Method for Testing a Defect of a Memory Module and a Memory System
7 Oct 21
The present application discloses an apparatus for testing defects of a memory module comprises a central buffer for generating a test write command and a test read command to indicate testing to a target address in a memory module; and a data buffer coupled to the central buffer to receive the test write command and the test read command; the data buffer is configured to, in response to the test write command, use target data as repair data corresponding to the target address, and write the target data into the memory module; and, in response to the test read command, to read target data from the target address and compare the target data with the repair data, and to send to the central buffer a comparison result of the target data and the repair data; the central buffer is further configured to record the target address as a tested address when generating the test write command, and determine whether to add the tested address to defective address information based on the comparison result associated with the tested address, defective address information is to indicate one or more defective memory addresses in the memory module.
Gang SHAN, Yong ZHANG
Filed: 2 Jul 20
Utility
Apparatus and Method for Repairing a Defect of a Memory Module, and a Memory System
7 Oct 21
The present application discloses an apparatus for repairing a defect of a memory module, comprises: a central buffer having an address recording module for recording defective address information indicating one or more defective memory addresses in the memory module; the central buffer is configured to receive an access command for accessing a target address in the memory module from a memory interface, and to determine whether to generate a repair access command for repairing the target address according to a comparison result; and a data buffer having a data recording module for recording repair data; wherein the data buffer is coupled between the memory interface and the memory module to buffer data interacted therebetween, and is coupled to the central buffer to receive the access command or the repair access command; the data buffer is configured to write target data associated with the access command into the data recording module as repair data corresponding to a target address according to the repair access command, or read repair data from the data recording module as target data corresponding to a target address.
Gang SHAN, Yong ZHANG
Filed: 28 Jun 20
Utility
Memory Controller and Method for Monitoring Accesses to a Memory Module
30 Sep 21
The application discloses a memory controller coupled between a memory module and a host controller to control accesses of the host controller to the memory module.
Stephen TAI, Yi LI
Filed: 30 Nov 20
Utility
Computing device and neural network processor incorporating the same
28 Sep 21
The present application discloses a computing device and a neural network processor including the computing device.
Peng Wang, Chunyi Li
Filed: 18 May 20
Utility
Data conversion control apparatus, memory device and memory system
28 Sep 21
A data conversion control apparatus, comprising: at least one first interface each for coupling a first external interface, both of the first interface and the first external interface being in accordance with a predetermined physical interface standard, wherein data transmitted between the first interface and the first external interface is in accordance with a configurable application layer protocol; at least one second interface each for coupling a second external interface, wherein the second external interface is a memory interface in accordance with a predetermined memory interface standard, and the second interface is configurable to match the predetermined memory interface standard; and a data rebuild unit coupled between the at least one first interface and the at least one second interface, wherein the data rebuild unit is configured to rebuild data such that data can be transmitted in respective formats between the at least one first interface and the at least one second interface.
Gang Shan, Yi Li, Howard Chonghe Yang
Filed: 22 May 20
Utility
Method and Device for Pruning Convolutional Layer In Neural Network
16 Sep 21
The present application discloses a method and a device for pruning one or more convolutional layer in a neural network.
Yuanfei NIE, Zhen DONG, Huan FENG
Filed: 1 Dec 20
Utility
Phase locked loop-based power supply circuit and method, and chip
3 Aug 21
The present disclosure provides a phase locked loop-based power supply circuit and method, and a chip.
Gang Yan
Filed: 5 Nov 20
Utility
Processing Devices and Distributed Processing Systems
1 Jul 21
The present application pertains to a processing device or a distributed processing system using the processing device.
Gang SHAN, Ye YANG, Jingzhong YANG
Filed: 21 Dec 20
Utility
Test Device and Method with Built-in Self-test Logic
10 Jun 21
The present application discloses a test device and method with built-in self-test logic and a communication device.
Dan WANG, Ranran FAN, Xiao ZHU, Zhongyuan CHANG, Xin LIU
Filed: 15 Sep 20
Utility
Communication device and skew correction method thereof
13 Apr 21
The present disclosure provides a communication device and a skew correction method thereof.
Jun Ma, Dan Wang, Zhongyuan Chang, Xin Liu
Filed: 10 Jun 20
Utility
Delay circuit, clock control circuit and control method
30 Mar 21
A delay circuit, a clock control circuit and a control method are disclosed.
Bo Qu, Jinfu Chen, Lixin Jiang
Filed: 30 Dec 19