46 patents
Page 2 of 3
Utility
Package Substrate Structure and Method for Manufacturing Same
22 Sep 22
The present disclosure provides a package substrate structure and a method for manufacturing the same.
Meng MEI, Gang SHI, Peichun WANG, Guangfeng LI
Filed: 26 Aug 21
Utility
Memory Device with Split Power Supply Capability
15 Sep 22
A memory device includes a printed circuit board having a plurality of conductive layers; memory chips mounted over the printed circuit board, wherein the memory chips comprise at least a first number of memory chips and a second number of memory chips; a first power module mounted over the printed circuit board and for providing a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and a second power module mounted over the printed circuit board and for providing a second set of power supplies to the second number of memory chips through the plurality of conductive layers.
Christopher Cox
Filed: 15 Mar 21
Utility
Method and Device for Compressing Neural Network
26 May 22
A method for compressing a neural network includes: obtaining a neural network including J operation layers; compressing a jth operation layer with Kj compression ratios to generate Kj operation branches; obtaining Kj weighting factors; replacing the jth operation layer with the Kj operation branches weighted by the Kj weighting factors to generate a replacement neural network; performing forward propagation to the replacement neural network, a weighted sum operation being performed on Kj operation results generated by the Kj operation branches with the Kj weighting factors and a result of the weighted sum operation being used as an output of the jth operation layer; performing backward propagation to the replacement neural network, updated values of the Kj weighting factors being calculated based on a model loss; and determining an operation branch corresponding to the maximum value of the updated values of the Kj weighting factors as a compressed jth operation layer.
Zhen DONG, Yuanfei NIE, Huan FENG
Filed: 19 Nov 21
Utility
Method and Device for Compressing Neural Network
26 May 22
A method for compressing a neural network includes: obtaining a neural network including a plurality of parameters to be compressed; dividing the parameters into J blocks; compressing a jth block with Kj compression ratios to generate Kj operation branches; obtaining Kj weighting factors; replacing the jth block with the Kj operation branches weighted by the Kj weighting factors to generate a replacement neural network; performing forward propagation to the replacement neural network, a weighted sum operation being performed on Kj operation results generated by the Kj operation branches with the Kj weighting factors and a result of the operation being used as an output; performing backward propagation to the replacement neural network, updated values of the Kj weighting factors being calculated based on a model loss; and determining an operation branch corresponding to the maximum value of the updated values of the Kj weighting factors as a compressed jth block.
Zhen DONG, Yuanfei NIE, Huan FENG
Filed: 22 Nov 21
Utility
Method for Testing Electrical Performance of Packaged Chip
12 May 22
The application discloses a method for manufacturing an electrical performance test structure of packaged chip, and a method for testing electrical performance of packaged chip, including: providing a first wafer and a second wafer, forming a top metal layer on the first wafer and the second wafer respectively, forming bumps on part of the top metal layer of the first wafer and on part of the top metal layer of the second wafer respectively, removing the top metal layer that is not directly beneath the bumps in the first wafer, and completely retaining the top metal layer in the second wafer, and packaging the first wafer to a first die and packaging the second wafer to a second die, wherein the second die is used as a test structure, and the electrical performance of the second die is used as a reference for electrical performance of the first die.
Meng MEI, Gang SHI, Peichun WANG, Guangfeng LI
Filed: 15 May 20
Utility
Package Substrate and Manufacturing Method Thereof
5 May 22
A package substrate and a manufacturing method thereof, the method including: forming a package substrate by a first dielectric layer formed by weaving at least fiberglass of a first width and a second dielectric layer formed by weaving at least fiberglass of a second width.
Meng MEI, Gang SHI, Peichun WANG, Guangfeng LI
Filed: 15 May 20
Utility
Computing System and Method for Sharing Device Memories of Different Computing Devices
21 Apr 22
A computing system includes a host computing device and a slave computing device.
Ye YANG, Jingzhong YANG, Gang SHAN
Filed: 26 Aug 21
Utility
Asymmetrical I/o Structure
24 Feb 22
An asymmetrical I/O structure is provided.
Xiong ZHANG, Chunlai SUN, Juan DU, Gang SHI, Chonghe YANG
Filed: 19 Aug 21
Utility
Memory Controller and a Method for Controlling Access to a Memory Module
25 Nov 21
The application discloses a memory controller coupled between a memory module and a host controller to control access of the host controller to the memory module, comprising a central buffer coupled between the host controller and the memory module.
Yi LI, Gang SHAN, Guohui LI, Chunhui ZHANG
Filed: 21 May 21
Utility
Apparatus and Method for Testing a Defect of a Memory Module and a Memory System
7 Oct 21
The present application discloses an apparatus for testing defects of a memory module comprises a central buffer for generating a test write command and a test read command to indicate testing to a target address in a memory module; and a data buffer coupled to the central buffer to receive the test write command and the test read command; the data buffer is configured to, in response to the test write command, use target data as repair data corresponding to the target address, and write the target data into the memory module; and, in response to the test read command, to read target data from the target address and compare the target data with the repair data, and to send to the central buffer a comparison result of the target data and the repair data; the central buffer is further configured to record the target address as a tested address when generating the test write command, and determine whether to add the tested address to defective address information based on the comparison result associated with the tested address, defective address information is to indicate one or more defective memory addresses in the memory module.
Gang SHAN, Yong ZHANG
Filed: 2 Jul 20
Utility
Apparatus and Method for Repairing a Defect of a Memory Module, and a Memory System
7 Oct 21
The present application discloses an apparatus for repairing a defect of a memory module, comprises: a central buffer having an address recording module for recording defective address information indicating one or more defective memory addresses in the memory module; the central buffer is configured to receive an access command for accessing a target address in the memory module from a memory interface, and to determine whether to generate a repair access command for repairing the target address according to a comparison result; and a data buffer having a data recording module for recording repair data; wherein the data buffer is coupled between the memory interface and the memory module to buffer data interacted therebetween, and is coupled to the central buffer to receive the access command or the repair access command; the data buffer is configured to write target data associated with the access command into the data recording module as repair data corresponding to a target address according to the repair access command, or read repair data from the data recording module as target data corresponding to a target address.
Gang SHAN, Yong ZHANG
Filed: 28 Jun 20
Utility
Memory Controller and Method for Monitoring Accesses to a Memory Module
30 Sep 21
The application discloses a memory controller coupled between a memory module and a host controller to control accesses of the host controller to the memory module.
Stephen TAI, Yi LI
Filed: 30 Nov 20
Utility
Method and Device for Pruning Convolutional Layer In Neural Network
16 Sep 21
The present application discloses a method and a device for pruning one or more convolutional layer in a neural network.
Yuanfei NIE, Zhen DONG, Huan FENG
Filed: 1 Dec 20
Utility
Processing Devices and Distributed Processing Systems
1 Jul 21
The present application pertains to a processing device or a distributed processing system using the processing device.
Gang SHAN, Ye YANG, Jingzhong YANG
Filed: 21 Dec 20
Utility
Test Device and Method with Built-in Self-test Logic
10 Jun 21
The present application discloses a test device and method with built-in self-test logic and a communication device.
Dan WANG, Ranran FAN, Xiao ZHU, Zhongyuan CHANG, Xin LIU
Filed: 15 Sep 20
Utility
Computing Device and Neural Network Processor Incorporating the Same
25 Nov 20
The present application discloses a computing device and a neural network processor including the computing device.
Peng WANG, Chunyi LI
Filed: 17 May 20
Utility
Data Conversion Control Apparatus, Memory Device and Memory System
25 Nov 20
A data conversion control apparatus, comprising: at least one first interface each for coupling a first external interface, both of the first interface and the first external interface being in accordance with a predetermined physical interface standard, wherein data transmitted between the first interface and the first external interface is in accordance with a configurable application layer protocol; at least one second interface each for coupling a second external interface, wherein the second external interface is a memory interface in accordance with a predetermined memory interface standard, and the second interface is configurable to match the predetermined memory interface standard; and a data rebuild unit coupled between the at least one first interface and the at least one second interface, wherein the data rebuild unit is configured to rebuild data such that data can be transmitted in respective formats between the at least one first interface and the at least one second interface.
Gang SHAN, Yi LI, Howard Chonghe YANG
Filed: 21 May 20
Utility
Apparatus and Method for Controlling Access to Memory Module
21 Oct 20
An apparatus controls access to a memory module coupled to a host controller via a data bus to exchange data with the host controller.
Yi LI, Gang SHAN, Howard Chonghe YANG
Filed: 12 Apr 20
Utility
Delay Circuit, Clock Control Circuit and Control Method
23 Sep 20
A delay circuit, a clock control circuit and a control method are disclosed.
Bo QU, Jinfu CHEN, Lixin JIANG
Filed: 29 Dec 19
Utility
Time-to-digital Converter and Phase Difference Detection Method
23 Sep 20
A time-to-digital converter and a phase difference detection method are disclosed.
Pengzhan ZHANG, Yong WANG, Yanhong LI, Yaomin WU, Zhongyuan CHANG
Filed: 2 Mar 20