34 patents
Utility
DCDC Converter, Integrated Circuit, and Target Voltage Generation Circuit
14 Dec 23
A direct current to direct current converter is disclosed that controls an output voltage based on an error signal between a feedback voltage and a target voltage.
Kenji AKATSUKI, Takaaki NOJIMA, Masaru NAKAMURA
Filed: 19 May 23
Utility
Active Clamp Flyback Converter and Control Ic
14 Dec 23
An active clamp flyback converter includes a main switch, a primary winding that is electrically connected in series with the main switch, a clamp switch that is electrically connected to a connection point between the main switch and the primary winding, a clamp capacitor that is connected in series with the clamp switch, and a controller that outputs a first ON signal to control the main switch and a second ON signal to control the clamp switch during a period when the main switch is off.
Shinji ASO
Filed: 23 May 23
Utility
zc48a6b04na8q3j j4001eo230zk6u2z28dquc7zunlfkwxk7som755d
12 Oct 23
A detector compares a drain voltage with a first threshold voltage and outputs a first detection signal.
Eunsuk LEE, Jungyul KIM, Masaaki SHIMADA, Shinji ASO, Mitsutomo YOSHINAGA, Hanju KANG
Filed: 7 Apr 22
Utility
ji7gfjixr lxlxy7atuvsc8f6e5mpus6o8h69i35ji8okktrqbm2nx93w5f
12 Oct 23
A detector compares a drain voltage with a first threshold voltage and outputs a first detection signal.
Eunsuk LEE, Kyusam CHOI, Jaekuk YU, Shinji ASO, Mitsutomo YOSHINAGA, Hanju KANG
Filed: 7 Apr 22
Utility
a910alpubc22xayt64f0qkjji13 qriplsast646j5kbnpn
28 Sep 23
A semiconductor device according to one or more embodiment may include: an IGBT region including a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type arranged on the first semiconductor region; a third semiconductor region of the first conductivity type arranged on the second semiconductor region; a fourth semiconductor region of the second conductivity type arranged on the first semiconductor region and opposite the second semiconductor region; and a control electrode that is arranged via an insulating film opposite the second semiconductor region; and a diode region comprising a fifth semiconductor region of the second conductivity type on the first semiconductor region.
Masayuki HANAOKA
Filed: 8 Dec 22
Utility
sxwcsgk6ko9mo ejpesqbay1rnq29o9h1d1kcugk7nt494
28 Sep 23
A light emitting device according to one or more embodiment is disclosed, which may include a blue LED, a first phosphor that is excited by light of the blue LED and emits green to yellow light, and a second phosphor that is excited by light of the blue LED and emits light with an emission peak wavelength greater than the emission peak wavelength of the first phosphor but 625 nm or less.
Yousuke UMETSU
Filed: 14 Mar 23
Utility
xc7fidqjtkxertnvp cvqyv4t484
27 Jul 23
A semiconductor device according to one or more embodiments may include: on a semiconductor substrate, a high voltage circuit region; a transistor element region; an isolation region that elementally isolates the transistor element region from the high voltage circuit region; and a capacitively coupled field plate including plural lines of conductors, wherein the capacitively coupled field plate is provided to extend circumferentially along an outer circumferential portion of the high voltage circuit region and across the transistor element region, in a plan view of the semiconductor device, and one or more dividing sections divides at least one of the plural lines of conductors in the capacitively coupled field plate to make the at least one line discontinuous.
Hironori AOKI
Filed: 31 Mar 22
Utility
v1q2p bx96vzy7ch4p8v1f8zvokgpsu8az01
27 Jul 23
A watchdog timer device according to one or more embodiments may include a mode setting unit that sets a first mode or a second mode.
Naohiko SHIMOYAMA
Filed: 28 Mar 23
Utility
qlfds7vlshlc3hdmlxl8c4dcauf 0vc
25 May 23
A semiconductor device according to one or more embodiments may include a drive circuit comprising: a gate control circuit that generates a gate control signal; a first resistor comprising a first electrode electrically connected to the gate control circuit and a second electrode; and a second resistor comprising a first electrode electrically connected to the gate control circuit and a second electrode that is not electrically connected to the second electrode of the first resistor; wherein the second resistor comprises a resistance value greater than that of the first resistor; an IGBT circuit comprising: a first IGBT cell electrically connected to the second electrode of the first resistor; and a second IGBT cell electrically connected to the second electrode of the second resistor.
Katsuyuki TORII
Filed: 24 Nov 21
Utility
781pyi6xze9wr84nunh ojcrfe207h00
27 Apr 23
A semiconductor device may include: a drift region of a first conductivity type; a base region of a second conductivity type arranged on the drift region; an emitter region of the first conductivity type arranged on the base region; a field stop region of the first conductivity type arranged in contact with the drift region; a collector region of the second conductivity type in contact with the field stop region; a main gate electrode electrically insulated from the base region and the collector region; a control gate electrode electrically insulated from the base region and the collector region; a gate pad on the drift region; a first resistor electrically connected between the gate pad and the main gate electrode; and a second resistor electrically connected between the gate pad and the control gate electrode.
Katsuyuki TORII
Filed: 27 Oct 21
Utility
t101luhs3yx9x55u6vu372q1zat
27 Apr 23
An analog-to-digital converter is disclosed that converts an input analog potential to a digital conversion value.
Hideki Hayashi
Filed: 23 Dec 21
Utility
nst0ciwmfr0aw443v5eqmop5f55u271ut5p4biw6uvw3hb43sk9f08wh
23 Mar 23
A semiconductor is disclosed that may include: a first drift region; a base region arranged on the first semiconductor layer; a source region arranged on the base region; a main electrode electrically connected to the source region; and a gate electrode structure that penetrates the source region and base region and reaches the first drift region, wherein the gate electrode structure comprises: a gate electrode; and an insulating material that insulates the gate electrode from the first drift region and the base region; and a field plate structure reaching the first drift region deeper than the gate electrode structure, wherein the field plate structure comprises: a field plate; a resistive part that electrically connects the main electrode to the field plate; and an insulating material that insulates the field plate and the resistive part section from the first drift region and the base region.
Taro KONDO, Shunsuke FUKUNAGA, Bungo TANAKA, Jun YASUHARA
Filed: 20 Sep 21
Utility
fo4xb6dabvht309s uv3p7vctf0teys64aqb39bw0fnpiuep
2 Mar 23
A semiconductor device according to one or more embodiments is disclosed that may include a first substrate comprising a single-crystalline SiC substrate; a second substrate comprising a polycrystalline SiC substrate; and an interface layer sandwiched between the first substrate and the second substrate and comprising at least elements of phosphorus and chromium.
Toru YOSHIE
Filed: 25 Aug 21
Utility
331g20xa3pjiydz05357th
2 Mar 23
A semiconductor device and a method of manufacturing a semiconductor device according to one or more embodiments are disclosed.
Toru YOSHIE
Filed: 5 Oct 22
Utility
te3qlv8b6p59ojyg 2pjifgrfz9ulsonmgl
5 Jan 23
A dimming agent according to one or more embodiments is disclosed that may include at least one of terbium, praseodymium, manganese, titanium.
Yousuke UMETSU, Kazuyoshi HAGA
Filed: 14 Sep 22
Utility
4ef4krrvues0iw645aj157nleiz0commfbsm00aq6c1p8kjy9elbg znom
29 Dec 22
A first semiconductor region, a second semiconductor region, and a third semiconductor region are arranged in layers.
Bungo TANAKA
Filed: 29 Jun 21
Utility
v5enju4vojdwzth6fl0kjrfk7
27 Oct 22
An abnormality detection circuit and method of detecting an abnormality in a CPU is disclosed that may include counting a count value from an initial value to a timeout value; storing a seed value readable from the CPU; generating a key value for verification by performing a specified arithmetic processing on the seed value; waiting for a key value to be written by the CPU; comparing the key value written by the CPU with the key value for verification; and when the count value is equal to the timeout value without the counter being reset, in response to the key value and the key value for verification matching, resetting the counter and storing the seed value to be determined at the time of resetting the counter in the seed value storage section.
Naohiko SHIMOYAMA
Filed: 8 Jul 22
Utility
y910qxuy2vshzeffhsi0s4493s5jbqzunfwsb peeog2sv8
15 Sep 22
An integrated circuit for digitally controlling a critical mode power factor correction (PFC) circuit according to one or more embodiments may include: an output voltage detector and a switching current detector; an A/D converter and a sample and hold circuit that perform analog-to-digital conversion of an output signal of the output voltage detector and the switching current detector; an arithmetic unit that performs calculation based on the output signal of the A/D converter and generates a pulse signal to turn on/off a switching device of the PFC circuit; a correction value calculator that calculates, based on a switching frequency of the PFC circuit, a correction value for linearly correcting the output signal of the A/D converter; and an adder that adds the correction value to the output signal of the A/D converter to correct the output signal of the A/D converter and inputs the corrected output signal to the arithmetic unit.
Osamu OHTAKE, Ryuichi FURUKOSHI
Filed: 9 Mar 22
Utility
ds4cuxqkyj30q915y01sw0lydzd 7g6v487kng270k4gxp3d
25 Aug 22
A method may include detecting an output voltage of the output smoothing capacitor in the bridgeless interleaved power factor correction circuit of a critical mode, comparing the detected output voltage with a reference voltage, controlling the first and the second half-bridge circuits included in the bridgeless interleaved power factor correction circuit of the critical mode to be on and off based on an error signal between the output voltage and the predetermined reference voltage, measuring ON time of a synchronous rectification switch operation of the first half-bridge circuit by measuring a time period between OFF timing of an active switch of the first half-bridge circuit and output of a differentiation signal generated by a differentiation circuit included in the bridgeless interleaved power factor correction circuit of the critical mode; and assigning the measured time to next ON time of the synchronous rectification switch operation of the second half-bridge circuit.
Osamu OHTAKE, Ryuichi FURUKOSHI
Filed: 22 Feb 22
Utility
rvnrl1x g4az7m2dyrik3pwof4s4tw90p36g0n
14 Jul 22
A semiconductor device is disclosed that includes a group of trenches positioned in active region inside a first semiconductor region.
Taro KONDO
Filed: 12 Jan 21