1434 patents
Page 3 of 72
Utility
Huffman Packing for Delta Compression
28 Dec 23
Huffman packing for delta compression is described.
Yaser ElSayed, Angel Serah, Jing Xie
Filed: 27 Jun 22
Utility
Noise Mitigation In Single-ended Links
28 Dec 23
An integrated circuit includes a first terminal for receiving a data signal, a second terminal for receiving an external reference voltage, a receiver, and a reference voltage generation circuit.
Ramon Mangaser, Karthik Gopalakrishnan, Andy Huei Chu, Pradeep Jayaraman
Filed: 7 Sep 23
Utility
Assigning Bit Budgets to Parallel Encoded Video Data
28 Dec 23
A technique for encoding video is provided.
Wei Gao, Gabor Sines, Ihab M. A. Amer, Crystal Yeong-Pian Sau, Feng Pan, Dong Liu
Filed: 22 Jun 22
Utility
Adaptive Thread Management for Heterogenous Computing Architectures
28 Dec 23
An apparatus and method for efficiently scheduling tasks in a dynamic manner to multiple cores that support a heterogeneous computing architecture.
Donny Yi, Indrani Paul, Ashwini Chandrashekhara Holla
Filed: 22 Jun 22
Utility
Live Profile-driven Cache Aging Policies
28 Dec 23
A technique for operating a cache is disclosed.
Christopher J. Brennan, Akshay Lahiry
Filed: 27 Jun 22
Utility
Technique to Enable Simultaneous Use of On-die Sram As Cache and Memory
28 Dec 23
A technique for operating a cache is disclosed.
Chintan S. Patel, Vydhyanathan Kalyanasundharam, Benjamin Tsien, Alexander J. Branover
Filed: 28 Jun 22
Utility
Allocation Control for Cache
28 Dec 23
A technique for operating a cache is disclosed.
Chintan S. Patel, Alexander J. Branover, Benjamin Tsien, Edgar Munoz, Vydhyanathan Kalyanasundharam
Filed: 28 Jun 22
Utility
Memory Controller with Pseudo-channel Support
28 Dec 23
A data processor accesses a memory having a first pseudo channel and a second pseudo channel.
Hideki Kanayama, YuBin Yao
Filed: 24 Jun 22
Utility
Enabling Accelerated Processing Units to Perform Dataflow Execution
28 Dec 23
Methods and systems are disclosed for performing dataflow execution by an accelerated processing unit (APU).
Johnathan Robert Alsop, Karthik Ramu Sangaiah, Anthony T. Gutierrez
Filed: 28 Jun 22
Utility
Smart Feedback Design for Verification
28 Dec 23
Techniques for implementing a smart feedback design for verification that reduce production and verification time by enabling a verification system to perform piecemeal verification of components of a circuit design selectively, accurately, and exhaustively before a final, overall circuit design is completed are disclosed.
David Akselrod
Filed: 22 Jun 22
Utility
Channel Routing for Simultaneous Switching Outputs
28 Dec 23
A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel.
Xuan Chen, Chih-Hua Hsu, Pradeep Jayaraman, Abdussalam Aburwein
Filed: 24 Jun 22
Utility
Binning Pass with Hierarchical Depth Data Determination
28 Dec 23
Currently with performing a visibility pass for two or more coarse bins of an image, a processing system determines a bounding box for a primitive to be rendered for the image based on a bottom left-most point of the primitive and a top right-most point of the primitive.
Kiia K. Kallio, Miikka Kangasluoma, Jan Achrenius
Filed: 28 Jun 22
Utility
Method and Apparatus for Recovering Regular Access Performance In Fine-grained Dram
28 Dec 23
A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit.
Sriseshan Srikanth, Vignesh Adhinarayanan, Jagadish B. Kotra, Sergey Blagodurov
Filed: 31 Aug 23
Utility
Method and Apparatus for Training Memory
21 Dec 23
A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer.
Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani, Tsun Ho Liu
Filed: 21 Jun 22
Utility
VLIW Dynamic Communication
21 Dec 23
In accordance with described techniques for VLIW Dynamic Communication, an instruction that causes dynamic communication of data to at least one processing element of a very long instruction word (VLIW) machine is dispatched to a plurality of processing elements of the VLIW machine.
Sriseshan Srikanth, Karthik Ramu Sangaiah, Anthony Thomas Gutierrez, Vedula Venkata Srikant Bharadwaj, John Kalamatianos
Filed: 17 Jun 22
Utility
Approach for Processing Near-memory Processing Commands Using Near-memory Register Definition Data
21 Dec 23
An approach is provided for processing near-memory processing commands, e.g., PIM commands, using PIM register definition data that defines multiple combinations of source and/or destination registers to be used to process PIM commands.
Shaizeen Aga, Nuwan Jayasena
Filed: 21 Jun 22
Utility
Partial Sorting for Coherency Recovery
21 Dec 23
Devices and methods for partial sorting for coherence recovery are provided.
Matthäus G. Chajdas, Christopher J. Brennan
Filed: 21 Jun 22
Utility
Balanced Throughput of Replicated Partitions In Presence of Inoperable Computational Units
21 Dec 23
An apparatus and method for efficiently managing balanced performance among replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects.
Ashish Jain, Sriram Sundaram, Christopher Allan Poirier, Samuel D. Naffziger
Filed: 20 Jun 22
Utility
Neural Network Activation Scaled Clipping Layer
21 Dec 23
Activation scaled clipping layers for neural networks are described.
Hai Xiao, Adam H Li, Harris Eleftherios Gasparakis
Filed: 20 Jun 22
Utility
Host-level Error Detection and Fault Correction
21 Dec 23
A processing system includes a processing device coupled to a memory configured to check for and correct faults in requested data.
Sudhanva Gurumurthi, Vilas Sridharan
Filed: 16 Jun 22