1434 patents
Page 5 of 72
Utility
Method And Apparatus For a Page-Local Delta-Based Prefetcher
23 Nov 23
A method includes recording a first set of consecutive memory access deltas, where each of the consecutive memory access deltas represents a difference between two memory addresses accessed by an application, updating values in a prefetch training table based on the first set of memory access deltas, and predicting one or more memory addresses for prefetching responsive to a second set of consecutive memory access deltas and based on values in the prefetch training table.
Susumu Mashimo, John Kalamatianos
Filed: 19 Apr 23
Utility
Address Translation Services Buffer
23 Nov 23
An address translation buffer or ATB is provided for emulating or implementing the PCIe (Peripheral Component Interface Express) ATS (Address Translation Services) protocol within a PCIe-compliant device.
Philip Ng, Vinay Patel
Filed: 31 Jul 23
Utility
Pipeline Delay Elimination with Parallel Two Level Primitive Batch Binning
23 Nov 23
A technique for rendering is provided.
Michael John Livesley, Ruijin Wu
Filed: 13 Dec 22
Utility
Sharing Package Pins In a Multi-chip Module (MCM)
16 Nov 23
A semiconductor package includes multiple dies that share the same package pin.
YULEI SHEN, TYRONE TUNG HUANG, CHEN-KUAN HONG
Filed: 13 May 22
Utility
Memory Calibration System and Method
16 Nov 23
A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed.
Jing Wang, Kedarnath Balakrishnan, Kevin M. Brandl, James R. Magro
Filed: 17 May 23
Utility
Performing Operations for Handling Data using Processor in Memory Circuitry in a High Bandwidth Memory
9 Nov 23
An electronic device includes a processor and a memory separate from the processor.
Jagadish B. Kotra, Marko Scrbak
Filed: 3 May 22
Utility
Approach for Skipping Near-memory Processing Commands
9 Nov 23
An approach is provided for skipping, i.e., not processing and/or deleting, near-memory processing commands when one or more skip criteria are satisfied.
Shaizeen Aga, Mohamed Assem Abd ElMohsen Ibrahim
Filed: 9 May 22
Utility
Platform Power Manager for Rack Level Power and Thermal Constraints
2 Nov 23
Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode.
Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
Filed: 23 Jun 23
Utility
Device and Method for Efficient Transitioning to and from Reduced Power State
2 Nov 23
A processing device and method for efficient transitioning to and from a reduced power state is provided.
Mihir Shaileshbhai Doctor, Alexander J. Branover, Benjamin Tsien, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry
Filed: 21 Apr 23
Utility
Compiler Directed Fine Grained Power Management
2 Nov 23
Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler.
Vedula Venkata Srikant Bharadwaj, Shomit Das, Anthony T. Gutierrez, Vignesh Adhinarayanan
Filed: 3 Jul 23
Utility
Real Time Profile Switching for Memory Overclocking
2 Nov 23
Profile switching for memory overclocking is described.
Grant Evan Ley, Jayesh Hari Joshi, Amitabh Mehra, Jerry Anton Ahrens, Joshua Taylor Knight, Anil Harwani, William Robert Alverson
Filed: 29 Apr 22
Utility
Real Time Workload-Based System Adjustment
2 Nov 23
Real time workload-based system adjustment is described.
Anil Harwani, William Robert Alverson, Amitabh Mehra, Jerry Anton Ahrens, Grant Evan Ley, Joshua Taylor Knight
Filed: 29 Apr 22
Utility
Identifying Memory System Sensitivity to Timing Parameters
2 Nov 23
Various timing parameter values for a memory system are changed and a workload is run using the changed timing parameter values resulting in workload performance values.
Joshua Taylor Knight, Jayesh Hari Joshi, Anil Harwani, Grant Evan Ley, Jerry Anton Ahrens, William Robert Alverson, Amitabh Mehra
Filed: 29 Apr 22
Utility
Method and Apparatus of Integrating Memory Stacks
2 Nov 23
An apparatus and method for performing memory operations in memory stacks comprising receiving a memory operation request at a first memory controller, where the first memory controller is in included in a first logic die in communication with a first memory die of a first memory technology, from a processor via a first bus.
Dmitri Yudanov, Michael Ignatowski
Filed: 13 Mar 23
Utility
Accelerating Neural Networks with One Shot Skip Layer Pruning
2 Nov 23
Systems, methods, and devices for pruning a convolutional neural network (CNN).
Arun Coimbatore Ramachandran, Chandra Kumar Ramasamy, Prakash Sathyanath Raghavendra, Keerthan Shagrithaya
Filed: 30 Jun 23
Utility
Method and Apparatus for Performing High Speed Parallel Locally Order Clustering for a Bounding Volume Hierarchy
2 Nov 23
A technique for building a bounding volume hierarchy is disclosed.
John Alexandre Tsakok
Filed: 30 Sep 22
Utility
Transmission of Address Translation Type Packets
26 Oct 23
Apparatuses, systems and methods for routing requests and responses targeting a shared resource.
Kostantinos Danny Christidis
Filed: 13 Jun 23
Utility
Alternative Protocol Over Physical Layer
26 Oct 23
A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol.
Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
Filed: 30 Jun 23
Utility
Mixed Signal Feedback Design for Verification
26 Oct 23
Techniques for implementing a mixed signal feedback design for verification that reduce production and verification time by enabling piecemeal verification of components of a circuit design selectively, accurately, and exhaustively before a final, overall circuit design is completed are disclosed.
David Akselrod, Shi Han Zhang, Chun Fung Lam
Filed: 18 Nov 22
Utility
Dynamic Cache Bypass for Power Savings
26 Oct 23
A technique for operating a cache is disclosed.
Ashish Jain, Benjamin Tsien, Chintan S. Patel, Vydhyanathan Kalyanasundharam, Shang Yang
Filed: 26 Apr 22