1150 patents
Page 5 of 58
Utility
Methods and systems for removing expired flow table entries using an extended packet processing pipeline
14 Nov 23
A network appliance can be configured for storing a plurality of flow table entries in a flow table of a match-action pipeline, wherein the match-action pipeline is implemented via a packet processing circuit configured to process a plurality of network traffic flows associated with the plurality of flow table entries.
Sameer Kittur Subrahmanya, Murty Kota, Tuyen Quoc, Harinadh Nagulapalli
Filed: 29 Aug 22
Utility
Fine-grained conditional dispatching
7 Nov 23
Techniques for executing workgroups are provided.
Alexandru Dutu, Marcus Nathaniel Chow, Matthew D. Sinclair, Bradford M. Beckmann, David A. Wood
Filed: 24 Sep 20
Utility
Bond pads for low temperature hybrid bonding
7 Nov 23
Various chip stacks and methods and structures of interconnecting the same are disclosed.
Priyal Shah, Milind S. Bhagavat
Filed: 2 Mar 21
Utility
Region based directory scheme to adapt to large cache sizes
7 Nov 23
Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed.
Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan, Eric Christopher Morton, Elizabeth M. Cooper, Ravindra N. Bhargava
Filed: 13 Sep 21
Utility
Phase shedding based on phase efficiency determined by pulse width modulator switching of voltage regulator field effect transistors
7 Nov 23
A method of operating a multiphase power supply includes identifying a least efficient phase of a plurality of phases in the multiphase power supply based on a comparison of a pulse width for each phase in the plurality of phases, and decreasing an amount of power supplied to a load by the identified least efficient phase.
Martin McAfee, David L Wigton
Filed: 23 Sep 20
Utility
Refresh management list for DRAM
7 Nov 23
A memory controller includes a command queue having a first input for receiving memory access requests, and a memory interface queue having an output for coupling to a memory channel adapted for connecting to at least one dynamic random access memory (DRAM) module.
Kevin M. Brandl
Filed: 21 Sep 20
Utility
Hardware security hardening for processor devices
7 Nov 23
A method of packet attribute confirmation includes receiving, at a command processor of a parallel processor, a command packet including a received packet attribute, such as a packet size, of the command packet.
Harry J. Wise, Alexander Fuad Ashkar, Manu Rastogi
Filed: 25 Sep 20
Utility
Job scheduling using reinforcement learning
31 Oct 23
Systems, methods, and techniques utilize reinforcement learning to efficiently schedule a sequence of jobs for execution by one or more processing threads.
Thomas Daniel Perry, Steven Tovey, Mehdi Saeedi, Andrej Zdravkovic, Zhuo Chen
Filed: 18 Nov 21
Utility
Scheme for enabling die reuse in 3D stacked products
31 Oct 23
Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed.
John J. Wuu, Milind S. Bhagavat, Brett P. Wilkerson, Rahul Agarwal
Filed: 27 Sep 19
Utility
Channel training using a replica lane
31 Oct 23
Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described.
Stanley Ames Lackey, Jr., Damon Tohidi, Gerald R. Talbot, Edoardo Prete
Filed: 14 Aug 20
Utility
Write hardware training acceleration
31 Oct 23
A memory includes a link training circuit with a pseudo-random bit sequence (PRBS) generator and a burst error detection counter.
Aaron D Willey, Karthik Gopalakrishnan
Filed: 30 Jun 22
Utility
Multi-level cache coherency protocol for cache line evictions
31 Oct 23
Disclosed are examples of a system and method to communicate cache line eviction data from a CPU subsystem to a home node over a prioritized channel and to release the cache subsystem early to process other transactions.
Amit Apte, Ganesh Balakrishnan, Ann Ling, Vydhyanathan Kalyanasundharam
Filed: 22 Dec 20
Utility
Computer processing devices with dynamic shared cache line copy retention policy selection
31 Oct 23
Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments.
John Kelley, Paul Moyer
Filed: 8 Nov 21
Utility
Dynamic application of software data caching hints based on cache test regions
31 Oct 23
A processor applies a software hint policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different software hint policy for data associated with cache entries in each region of the cache.
Paul Moyer
Filed: 28 Oct 21
Utility
Adaptive quantization for neural networks
31 Oct 23
Methods, devices, systems, and instructions for adaptive quantization in an artificial neural network (ANN) calculate a distribution of ANN information; select a quantization function from a set of quantization functions based on the distribution; apply the quantization function to the ANN information to generate quantized ANN information; load the quantized ANN information into the ANN; and generate an output based on the quantized ANN information.
Daniel I. Lowell, Sergey Voronov, Mayank Daga
Filed: 20 Dec 17
Utility
Broadcast synchronization for dynamically adaptable arrays
31 Oct 23
An array processor includes processor element arrays (PEAs) distributed in rows and columns.
Sateesh Lagudu, Arun Vaidyanathan Ananthanarayan, Michael Mantor, Allen H. Rush
Filed: 10 Dec 21
Utility
System and method for coalesced multicast data transfers over memory interfaces
31 Oct 23
Methods and apparatuses to control digital data transfer via a memory channel between a memory module and a processor are disclosed.
Johnathan Alsop, Nuwan Jayasena, Shaizeen Aga, Andrew McCrabb
Filed: 31 Mar 21
Utility
Error reporting for non-volatile memory modules
24 Oct 23
A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module.
James R. Magro, Kedarnath Balakrishnan, Vilas Sridharan
Filed: 14 Jul 22
Utility
Hardware-software collaborative address mapping scheme for efficient processing-in-memory systems
24 Oct 23
Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts.
Mahzabeen Islam, Shaizeen Aga, Nuwan Jayasena, Jagadish B. Kotra
Filed: 16 May 22
Utility
Cache management based on reuse distance
24 Oct 23
A cache of a processor includes a cache controller to implement a cache management policy for the insertion and replacement of cache lines of the cache.
Jieming Yin, Subhash Sethumurugan, Yasuko Eckert
Filed: 14 Oct 19