1150 patents
Page 8 of 58
Utility
Method and apparatus for a dram cache tag prefetcher
19 Sep 23
Devices and methods for cache prefetching are provided.
Jagadish B. Kotra, Marko Scrbak, Matthew Raymond Poremba
Filed: 31 Mar 21
Utility
Cuckoo filters and cuckoo hash tables with biasing, compression, and decoupled logical sparsity
19 Sep 23
A method includes, for each key of a plurality of keys, identifying from a set of buckets a first bucket for the key based on a first hash function, and identifying from the set of buckets a second bucket for the key based on a second hash function.
Alexander D. Breslow, Nuwan S. Jayasena
Filed: 17 Aug 18
Utility
Method and apparatus for recovering regular access performance in fine-grained DRAM
12 Sep 23
A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit.
Sriseshan Srikanth, Vignesh Adhinarayanan, Jagadish B. Kotra, Sergey Blagodurov
Filed: 13 Dec 21
Utility
Noise mitigation in single ended links
12 Sep 23
A data transmission system includes a first circuit, a second circuit, and a reference voltage generation circuit.
Ramon Mangaser, Karthik Gopalakrishnan, Andy Huei Chu, Pradeep Jayaraman
Filed: 8 Dec 21
Utility
Efficient rank switching in multi-rank memory controller
12 Sep 23
A data processor includes a staging buffer, a command queue, a picker, and an arbiter.
Guanhao Shen, Ravindra Nath Bhargava
Filed: 24 Jun 21
Utility
Distributed geometry
12 Sep 23
Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed.
Todd Martin, Tad Robert Litwiller, Nishank Pathak, Randy Wayne Ramsey
Filed: 29 Sep 21
Utility
Cache allocation policy
12 Sep 23
A cache includes an upstream port, a downstream port, a cache memory, and a control circuit.
Chintan S. Patel, Girish Balaiah Aswathaiya
Filed: 28 Dec 21
Utility
Cache line coherence state downgrade
12 Sep 23
Techniques for performing cache operations are provided.
Paul J. Moyer
Filed: 29 Oct 21
Utility
Method and apparatus for maintaining stable operation of servers in a data center
5 Sep 23
A method and apparatus for managing overclocking in a data center includes determining a frequency limit of a first processor of a first server in the data center.
Amitabh Mehra, Jeffrey N. Burley, Anil Harwani
Filed: 23 Dec 19
Utility
Signalling for heterogeneous memory systems
5 Sep 23
A memory controller selects from among a plurality of memory access commands including volatile memory reads, volatile memory writes, non-volatile memory reads, and non-volatile memory writes.
James R. Magro, Kedarnath Balakrishnan
Filed: 23 Aug 21
Utility
Self-regulating power management for a neural network system
5 Sep 23
A neural network runs a known input data set using an error free power setting and using an error prone power setting.
Andrew G. Kegel, David A. Roberts
Filed: 4 Apr 22
Utility
Bounding volume hierarchy traversal
5 Sep 23
A technique for performing ray tracing operations is provided.
Skyler Jonathon Saleh, Ruijin Wu
Filed: 18 Dec 20
Utility
High-speed die connections using a conductive insert
5 Sep 23
A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.
Rahul Agarwal
Filed: 10 Dec 20
Utility
Semi-sorting compression with encoding and decoding tables
22 Aug 23
A data processing platform, method, and program product perform compression and decompression of a set of data items.
Alexander D. Breslow, Nuwan Jayasena, John Kalamatianos
Filed: 18 Apr 22
Utility
Context partitioning of branch prediction structures
22 Aug 23
A processor core executes a first process.
Marius Evers, David Kaplan
Filed: 1 May 18
Utility
Hardware assisted fine-grained data movement
22 Aug 23
A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit.
Muhammad Amber Hassaan, Anirudh Mohan Kaushik, Sooraj Puthoor, Gokul Subramanian Ravi, Bradford Beckmann, Ashwin Aji
Filed: 19 Mar 20
Utility
Programmable error correction code encoding and decoding logic
22 Aug 23
A memory module includes logic elements that are configurable to a particular ECC implementation.
Ross V. La Fetra
Filed: 9 Dec 20
Utility
Precise shadowing and adjustment of on-die timers in low power states
22 Aug 23
An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal.
Benjamin Tsien, Pravesh Gupta
Filed: 24 Jun 21
Utility
Compiler directed fine grained power management
15 Aug 23
Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler.
Vedula Venkata Srikant Bharadwaj, Shomit N. Das, Anthony T. Gutierrez, Vignesh Adhinarayanan
Filed: 25 Sep 20
Utility
Migrating pages of memory accessible by input-output devices
15 Aug 23
An electronic device includes a memory, an input-output memory management unit (IOMMU), a processor that executes a software entity, and a page migration engine.
Philip Ng, Nippon Raval
Filed: 29 Dec 20