22699 patents
Page 40 of 1135
Utility
Power Sharing by Multiple Expansion Cards
16 Nov 23
A first printed circuit board (PCB) comprises a first hardware interface, compatible with an interface standard, to couple the first PCB to a first socket of a second PCB, which further comprises a second socket, and first and second busses respectively coupled to the first and second sockets.
Vishal Narayanan, Anil Baby
Filed: 13 May 22
Utility
System and Method for Reducing Pellicle Rupture
16 Nov 23
The present disclosure is directed to a reinforcement system including: a framed pellicle including: a center part of a pellicle surrounded by a peripheral part of the pellicle, wherein the peripheral part is adhered to a pellicle frame; and an edge reinforcement for reinforcing the framed pellicle, positioned at a boundary between the center part of the framed pellicle and the pellicle frame.
Lance C. HIBBELER, John Ferdinand MAGANA, Chytra PAWASHE
Filed: 13 May 22
Utility
eln6cagui6zxzr2z6qohk7wqbkn78boclwb2hj86ek5
16 Nov 23
An offload analyzer analyzes a program for porting to a heterogenous computing system by identifying code objects for offloading to an accelerator.
Kermin E. ChoFleming, Jr., Egor A. Kazachkov, Daya Shanker Khudia, Zakhar A. Matveev, Sergey U. Kokljuev, Fabrizio Petrini, Dmitry S. Petrov, Swapna Raj
Filed: 23 Apr 21
Utility
z4270eo0dlv3p6abh20wle
16 Nov 23
A first storage location is to store a first floating-point data element.
Martin LANGHAMMER
Filed: 15 Jun 23
Utility
s3i0gan0k9p1aazqhu763892m1xy99qn67r7o082usvtteavf4qp9birbyy
16 Nov 23
An apparatus to facilitate enabling late-binding of security features via configuration security controller for accelerator devices is disclosed.
Alpa Trivedi, Steffen Schulz, Patrick Koeberl
Filed: 26 Jul 23
Utility
uqtjcf25pq0nuonullwf59n1dm8y5vj a5eeb3aueub7euvtdhco
16 Nov 23
Various examples relate to methods, computer programs, non-transitory computer-readable media, apparatuses, devices, computer systems, and a system for evaluating one or more hardware tracing records related to a hardware tracing operation or for processing a piece of software.
Stanislav BRATANOV
Filed: 27 Jul 23
Utility
lrnfsnp4bcvi2z28h7 h8i9m9glx
16 Nov 23
A graphics processor can include a processing cluster array including a plurality of processing clusters coupled with the plurality of memory controllers, each processing cluster of the plurality of processing clusters including a plurality of streaming multiprocessors, the processing cluster array configured for partitioning into a plurality of partitions.
Barnan Das, Mayuresh M. Varerkar, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Sherine Abdelhak, Praneetha Kotha, Neelay Pandit, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Abhishek R. Appu, Altug Koker, Joydeep Ray
Filed: 25 Jul 23
Utility
8dbhevfq8x1vr31qd7dbg2n6uyylqlpvlmltv9thafz nbl9a6p07
16 Nov 23
Embodiments of the invention include device packages and methods of forming such packages.
Omkar G. KARHADE, Nitin A. DESHPANDE, Debendra MALLIK, Bassam M. ZIADEH, Yoshihiro TOMITA
Filed: 25 Jul 23
Utility
bgnpbl4cpcu3dwxfgtzb5osvp3nyd4r4mk
16 Nov 23
Microelectronic assemblies, and related devices and methods, are disclosed herein.
Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
Filed: 25 Jul 23
Utility
6zjrj2p6cgvi5sl5b7ry12dgs omxyckx0opvbjgc65ytk3yf47y
16 Nov 23
Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package.
Jonathan ROSCH, Wei-Lun JEN, Cheng XU, Liwei CHENG, Andrew BROWN, Yikang DENG
Filed: 26 Jul 23
Utility
4iuf0qwvxa66yi7 v8rj5fmk5we2
16 Nov 23
Embodiments of a microelectronic assembly comprise a package substrate, a first integrated circuit (IC) die, a second IC die between the first IC die and the package substrate, a dielectric material between the first IC die and the package substrate, and a plurality of vias through the dielectric material, the vias coupling the first IC die and the package substrate.
Jong-Ru Guo, Zhen Zhou, Jason Mix, Chia-Pin Chiu, Zuoguo Wu
Filed: 12 May 22
Utility
ngfr4w7uaunbkmmvioiyov5qa7be7ec0fjxq6b2nz2qsfuv3itm3 jpr
16 Nov 23
Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described.
Robert L. BRISTOL, Kevin Lai LIN, Clifford J. ENGEL
Filed: 13 May 22
Utility
vxa3244oqqkrlf7t8plm99ym2w4rpbxpw576 yq9bomo
16 Nov 23
Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions.
Van H. Le, Timothy Jen, Vishak Venkatraman, Shailesh Kumar Madisetti, Cheng Tan, Harish Ganapathy, James Pellegren, Kamal H. Baloch, Abhishek Anil Sharma
Filed: 12 May 22
Utility
r92dziv18hktb03hegxrm7qdx
16 Nov 23
Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described.
Clifford J. ENGEL, Robert L. BRISTOL, Richard H. LIVENGOOD, Ilan RONEN, Kevin Lai LIN
Filed: 13 May 22
Utility
awybj0bls7ni1s7ynim8etnqf8gh51oqxk7anuqnd9846s3xwr2u7 uo
16 Nov 23
Techniques for forming thin film transistors (TFTs) having multilayer contact structures.
Abhishek Anil Sharma, Travis W. Lajoie, Van H. Le, Timothy Jen, Kamal H. Baloch, Mark Armstrong, Albert B. Chen, Moshe Dolejsi, Shailesh Kumar Madisetti, Afrin Sultana, Deepyanti Taneja, Vishak Venkatraman
Filed: 12 May 22
Utility
d6jge34vjvarkpurtxd4 205n8uyx58ozc6xnl089l
16 Nov 23
Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described.
Clifford J. ENGEL, Richard H. LIVENGOOD, Mauro J. KOBRINSKY, Robert L. BRISTOL, Akshit PEER
Filed: 13 May 22
Utility
dztwxjpl3l4uh7zuhwm8fm natu1skilybhn26t0h8esqilsi
16 Nov 23
Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric.
Abhishek Anil Sharma, Albert B. Chen, Mark Armstrong, Afrin Sultana, Van H. Le, Travis W. Lajoie, Shailesh Kumar Madisetti, Timothy Jen, Cheng Tan, Moshe Dolejsi, Vishak Venkatraman, Christopher Ryder, Deepyanti Taneja
Filed: 12 May 22
Utility
0yu1q34xpggwgaww4fb6o1i1ljs61g1p7uzoy3n4 pqcqjn0cit
16 Nov 23
An electronic system includes a first substrate including first solder bumps on a bottom surface, the first solder bumps having a first solder bump surface opposite from the bottom surface; a processor integrated circuit (IC) die including at least one processor mounted on a top surface of the first substrate; and a companion component to the processor IC.
Hazwani Jaffar, Poh Boon Khoo, Hooi San Lam, Jiun Hann Sir, Eng Huat Goh
Filed: 11 May 22
Utility
ihb1lfv4lek7abck n1y8o
16 Nov 23
Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure.
Cheng Tan, Yu-Wen Huang, Hui-Min Chuang, Xiaojun Weng, Nikhil J. Mehta, Allen B. Gardiner, Shu Zhou, Timothy Jen, Abhishek Anil Sharma, Van H. Le, Travis W. Lajoie, Bernhard Sell
Filed: 12 May 22
Utility
9zj0rbtqd9yr5zm jcbn8p
16 Nov 23
Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described.
Ehren MANNEBACH, Anh PHAN, Aaron LILAK, Willy RACHMADY, Gilbert DEWEY, Cheng-Ying HUANG, Richard SCHENKER, Hui Jae YOO, Patrick MORROW
Filed: 24 Jul 23