22699 patents
Page 48 of 1135
Utility
Apparatus and method for reusing manufacturing content across multi-chip packages
7 Nov 23
An apparatus includes a daughter die (DD) logic, and an arbitrator connected to the DD logic, and connected to an external testing device and a main die (MD) included in a multi-chip package (MCP).
Kalyana Kantipudi, Niraj Vasudevan
Filed: 10 Mar 22
Utility
Apparatus and method for controlling unit specific junction temperature with high temporal resolution for concurrent central processing unit (CPU) core testing
7 Nov 23
An apparatus includes a processor configured to control an automatic test equipment (ATE) to measure one or more parameters of a current test instance for testing a device under test (DUT), during execution of the current test instance on the DUT, and determine, based on the measured one or more parameters, one or more controls for controlling a temperature of a thermal head connected to the DUT so that a junction temperature of the DUT corresponds to a predetermined test temperature.
Mahesh Deshmane, Shoujie He, Christopher Wade Ackerman, Jacob Hales, Johnny Mata Vega, Joseph Zearing
Filed: 11 Mar 22
Utility
gyruyx9od1n6kbq19re1ela4 jxcgllmldb
7 Nov 23
The present disclosure relates to a method including providing a die including a cavity therein, wherein the die further may include a die fiducial on a top surface.
Vineeth Abraham, Wesley Morgan, Eric Moret, Paul Diglio, Srikant Nekkanty
Filed: 23 Sep 21
Utility
cv6ql1rw6vtulqida6p 7mm9ewu81xtn5275
7 Nov 23
Particular embodiments described herein provide for an electronic device that includes a first housing, where the first housing includes at least one first housing accelerometer and at least one first housing gyroscope, a second housing, where the second housing includes at least one second housing accelerometer and at least one second housing gyroscope, and a hinge.
Renjie Cui, Ke Han, Hemin Han, Lili Ma
Filed: 27 Dec 19
Utility
d3my2zuydeoy99398mrsvtrkp7lmvy tdxwhvoobhuo1w0wrm9y
7 Nov 23
A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload.
Ali Mohammad, Asma Al-Rawi, Ujjwal Gupta, Federico Ardanaz, Jonathan Eastep
Filed: 19 Oct 20
Utility
qumlgt44qyuiuubvvhinud803eksrwobjsitp0r25etqm38kosrt6u
7 Nov 23
Examples described herein relate to management of battery-use by one or more computing resources in the event of a power outage.
Francesc Guim Bernat, Suraj Prabhakaran, Karthik Kumar, Uzair Qureshi, Timothy Verrall
Filed: 29 Jul 19
Utility
wy61wuixtrfnqft22152zpzott1wlayk 3wge94zfk6va4wtrqif
7 Nov 23
In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.
Francesc Guim Bernat, Daniel Rivas Barragan, Kshitij A. Doshi, Mark A. Schmisseur
Filed: 4 Oct 21
Utility
czuoa2tezq80d8csh9ekapkkhff8tbmf0exzcm6tfv
7 Nov 23
Techniques and apparatus to provide for interactions between system components are described.
Kevan A. Lillie, Shlomi Lalush, Yaakov Dalsace, Adee Ofir Ran, Assaf Benhamou, David Golodni, Itay Tamir, Amir Laufer
Filed: 31 Mar 17
Utility
uqys2f5ofn62r8849 ay3yinbqdmi
7 Nov 23
Systems and methods for multi-modal user device authentication are disclosed.
Aleksander Magi, Barnes Cooper, Arvind Kumar, Julio Zamora Esquivel, Vivek Paranjape, William Lewis, Marko Bartscherer, Giuseppe Raffa
Filed: 23 Dec 19
Utility
r2bld7rxr8l3lz1nej 6s40yjkhbg1jid
7 Nov 23
Data integrity logic is executable by a processor to generate a data integrity code using a hardware-based secret.
Vincent R. Scarlata, Carlos V. Rozas, Baiju Patel, Barry E. Huntley, Ravi L. Sahita, Hormuzd M. Khosravi
Filed: 1 Jul 22
Utility
05gmu6rplxy1ni9dylhas4am0v84der
7 Nov 23
An apparatus and method for intelligent power virus protection in a processor.
Alexander Gendler, Sagi Meller, Gavri Berger, Igor Yanover
Filed: 27 Dec 19
Utility
pwdg 58c0r1zmdcifdzno0gr802npyoaiv8mgv9b5m2ubwknuzf1aj
7 Nov 23
Techniques are described for notebook hinge sensors.
James M. Okuley
Filed: 11 Jul 22
Utility
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7 Nov 23
The present disclosure describes an integrated circuit device that includes a digital signal processing (DSP) block.
Martin Langhammer, Simon Peter Finn
Filed: 26 Jun 20
Utility
tng32nl90k4h3izr3ry3msvcz5dx2fdnp5ip
7 Nov 23
An apparatus and method for performing dual concurrent multiplications of packed data elements.
Venkateswara Madduri, Elmoustapha Ould-Ahmed-Vall, Jesus Corbal, Mark Charney, Robert Valentine, Binwei Yang
Filed: 21 Sep 20
Utility
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2 Nov 23
Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die including a plurality of first circuits separated by scribe regions, and a plurality of second IC dies coupled to the first IC die, each one of the second IC dies being coupled proximate and adjacent to a corresponding one of the first circuits and conductively coupled to the corresponding one of the first circuits.
Satish Damaraju, Scott E. Siers, Altug Kokar, Wilfred Gomes, Mark C. Davis
Filed: 29 Apr 22
Utility
bljtzy29n3346wmigbnomed9p 3sq4dztsidjugyq9nil9oqblqz9u
2 Nov 23
A multiple die package is described that has an embedded bridge to connect the dies.
Yidnekachew S. MEKONNEN, Kemel AYGUN, Ravindranath V. MAHAJAN, Christopher S. BALDWIN, Rajasekaran SWAMINATHAN
Filed: 12 Jul 23
Utility
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2 Nov 23
An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer.
Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
Filed: 30 Jun 23
Utility
d18qunr4dodygzxufmayhmrgpz5x3mtbip3f7m850jb7pcxa7qfzjk5
2 Nov 23
Methods, apparatus, systems, and articles of manufacture to improve signal integrity performance in integrated circuit packages are disclosed.
Cemil Geyik, Kemal Aygun, Yidnekachew Mekonnen, Zhichao Zhang, Suddhasattwa Nad
Filed: 29 Apr 22
Utility
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2 Nov 23
Techniques for signal amplification for a photonic integrated circuit (PIC) die are disclosed.
Hiroki Tanaka, Bai Nie, Kristof Darmawikarta, Hari Mahalingam
Filed: 29 Apr 22
Utility
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2 Nov 23
An integrated circuit includes a package substrate that includes first and second electrical traces.
MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
Filed: 13 Apr 23