12 patents
Utility
Power Management Circuit In Low-power Double Data Rate Memory and Management Method Thereof
11 May 23
A power management circuit in a low-power double data rate memory is configured to manage a plurality of power supplies memory according to a reference voltage.
Shuenrun Seara JIAN
Filed: 25 Mar 22
Utility
Size Setting Method for Power Switch Transistor and System Thereof
11 May 23
A size setting method for a power switch transistor and a system thereof are proposed.
Shuenrun Seara JIAN
Filed: 22 Feb 22
Utility
Package Structure
4 Aug 22
A package structure includes a leadframe, a semiconductor die and a plastic package material.
Cheng-Fu YU, Kai-Jih SHIH, Chi-Yi WU
Filed: 19 Apr 22
Utility
Finfet Stack Gate Memory and Mehod of Forming Thereof
21 Apr 22
A method of forming a FinFET stack gate memory includes a nitride film forming step, a nitride film is formed on a memory cell area with a shallow trench isolation (STI) structure; a stripping step, a portion of the nitride film is stripped, the other portion of the nitride film is remained at the STI structure, and a STI oxide is disposed in the STI structure; a floating gate (FG) structure forming step, a tunnel oxide is disposed, and a first polysilicon is disposed to form a FG structure; an oxide-nitride-oxide (ONO) layer disposing step, a portion of the STI oxide is stripped, and an ONO layer is disposed; a removing step, a portion of the ONO layer is removed; a control gate (CG) structure forming step, a portion of the FG structure is removed, and a second polysilicon is disposed to form a CG structure.
Hsingya Arthur WANG
Filed: 28 Dec 21
Utility
Wafer-bonding Structure and Method of Forming Thereof
20 Jan 22
A method of forming a wafer-bonding structure includes a wafer-bonding step, a through silicon via (TSV) forming step, and a forming bonding pad step.
Hsingya Arthur WANG, Sheng-Yuan CHOU, Yu-Ting WANG, Wan-Yi CHANG
Filed: 29 Sep 21
Utility
Method and System for Detecting Abnormal Die
11 Nov 21
A method for detecting an abnormal die includes providing a wafer, determining the surrounding dies in accordance with a position of a target die on the wafer, calculating a difference between a value of an electrical characteristic of each of the surrounding dies and a value of an electrical characteristic of the target die to obtain the electrical characteristic deviations, ranking the absolute values of the electrical characteristic deviations to generate a ranking result, and determining the characteristic-related dies from the surrounding dies in accordance with the ranking result, determining a target-related area in accordance with the position of the target die, determining the target-related die from the characteristic-related dies in accordance with the target-related area and determining whether the target die is qualified in accordance with the target-related die.
Shou-Kang FAN, Lien-Sheng YANG
Filed: 31 Jul 20
Utility
Method of Forming Package Structure
30 Sep 21
A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step.
Cheng-Fu YU, Kai-Jih SHIH, Yi-Jung LIU
Filed: 2 Dec 20
Utility
Package Structure
30 Sep 21
A package structure includes a leadframe, a semiconductor die and a plastic package material.
Cheng-Fu YU, Kai-Jih SHIH, Yi-Jung LIU, Chi-Yi Wu
Filed: 2 Dec 20
Utility
Wafer-bonding Structure and Method of Forming Thereof
23 Sep 21
A method of forming a wafer-bonding structure includes a wafer-bonding step, a through silicon via (TSV) forming step, and a forming bonding pad step.
Hsingya Arthur WANG, Sheng-Yuan CHOU, Yu-Ting WANG, Wan-Yi CHANG
Filed: 20 Mar 20
Utility
Memory Inspecting Method and Memory Inspecting System
19 Aug 21
A memory inspecting method and a memory inspecting system are proposed.
PaiLu Dennis WANG, Lien-Sheng YANG
Filed: 2 Sep 20
Utility
Proximity Detection Method and Proximity Detection Keyboard
8 Jul 21
A proximity detection method is for detecting if a user is proximate to a proximity detection keyboard, and the proximity detection keyboard includes a plurality of electrodes and at least one grounding element, which is disposed correspondingly to the electrodes.
Huai-Tsu CHANG, Ku-Hsiung FENG, Chia-Hsien CHANG, Wen-Hsiang LIN
Filed: 4 Nov 20
Utility
Finfet Stack Gate Memory and Mehod of Forming Thereof
13 May 21
A method of forming a FinFET stack gate memory includes a nitride film forming step, a nitride film is formed on a memory cell area with a shallow trench isolation (STI) structure; a stripping step, a portion of the nitride film is stripped, the other portion of the nitride film is remained at the STI structure, and a STI oxide is disposed in the STI structure; a floating gate (FG) structure forming step, a tunnel oxide is disposed, and a first polysilicon is disposed to form a FG structure; an oxide-nitride-oxide (ONO) layer disposing step, a portion of the STI oxide is stripped, and an ONO layer is disposed; a removing step, a portion of the ONO layer is removed; a control gate (CG) structure forming step, a portion of the FG structure is removed, and a second polysilicon is disposed to form a CG structure.
Hsingya Arthur WANG
Filed: 11 Mar 20
- Prev
- 1
- Next
Patents are sorted by USPTO publication date, most recent first