8 patents
Utility
Controlling circuit for low-power low dropout regulator and controlling method thereof
12 Dec 23
A controlling circuit for a low-power low dropout regulator includes the low-power low dropout regulator, a current load detector and a bias current circuit.
Shuenrun Seara Jian
Filed: 4 May 22
Utility
Method of forming package structure
28 Mar 23
A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step.
Cheng-Fu Yu, Kai-Jih Shih, Yi-Jung Liu
Filed: 2 Dec 20
Utility
FINFET stack gate memory and method of forming thereof
28 Mar 23
A method of forming a FinFET stack gate memory includes a nitride film forming step, a nitride film is formed on a memory cell area with a shallow trench isolation (STI) structure; a stripping step, a portion of the nitride film is stripped, the other portion of the nitride film is remained at the STI structure, and a STI oxide is disposed in the STI structure; a floating gate (FG) structure forming step, a tunnel oxide is disposed, and a first polysilicon is disposed to form a FG structure; an oxide-nitride-oxide (ONO) layer disposing step, a portion of the STI oxide is stripped, and an ONO layer is disposed; a removing step, a portion of the ONO layer is removed; a control gate (CG) structure forming step, a portion of the FG structure is removed, and a second polysilicon is disposed to form a CG structure.
Hsingya Arthur Wang
Filed: 28 Dec 21
Utility
Method and system for detecting abnormal die
5 Jul 22
A method for detecting an abnormal die includes providing a wafer, determining the surrounding dies in accordance with a position of a target die on the wafer, calculating a difference between a value of an electrical characteristic of each of the surrounding dies and a value of an electrical characteristic of the target die to obtain the electrical characteristic deviations, ranking the absolute values of the electrical characteristic deviations to generate a ranking result, and determining the characteristic-related dies from the surrounding dies in accordance with the ranking result, determining a target-related area in accordance with the position of the target die, determining the target-related die from the characteristic-related dies in accordance with the target-related area and determining whether the target die is qualified in accordance with the target-related die.
Shou-Kang Fan, Lien-Sheng Yang
Filed: 31 Jul 20
Utility
High density 3D magnetic random access memory (MRAM) cell integration using wafer cut and transfer
24 May 22
In accordance with one embodiment, a method includes forming a cleavable donor substrate, the substrate including monocrystalline Si, forming a dielectric layer above the substrate in a film thickness direction, and cleaving the substrate into an upper portion having the dielectric layer and a lower portion.
Marcin Gajek, Kuk-Hwan Kim, Dafna Beery, Amitay Levi
Filed: 8 Jan 18
Utility
Memory inspecting method and memory inspecting system
7 Dec 21
A memory inspecting method and a memory inspecting system are proposed.
PaiLu Dennis Wang, Lien-Sheng Yang
Filed: 2 Sep 20
Utility
Internal latch circuit and method for generating latch signal thereof
7 Sep 21
An internal latch circuit having a plurality of low initial value D flip-flops, a plurality of high initial value D flip-flops, an internal latch signal generating circuit and a NAND gate, and a method for generating latch signal thereof is provided.
Kangmin Lee, Sangmin Jun, Youngjin Yoon, Seung Cheol Bae, Kwang Kyung Lee, Sun Byeong Yoon
Filed: 23 Oct 20
Utility
Clocked commands timing adjustments method in synchronous semiconductor integrated circuits
9 Nov 20
A method in a clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the clocked integrated circuit.
Steven Eaton, Matthew Manning
Filed: 28 Jan 19
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