32417 patents
Page 22 of 1621
Utility
Semiconductor Package and Method of Manufacturing the Same
4 Jan 24
A semiconductor package includes: a first semiconductor chip including first pads; a second semiconductor chip below the first semiconductor chip, the second semiconductor chip including a substrate including a front surface and an opposing rear surface, second pads on the front surface and in contact with the first pads, and through-electrodes electrically connected to the second pads and including protruding portions protruding from the rear surface of the substrate; through-via structures disposed around the second semiconductor chip and in contact with the first pads; a first dielectric layer extending along the rear surface of the substrate and side surfaces of the protruding portions of the through-electrodes; a second dielectric layer below the first dielectric layer and in a space between the protruding portions of the through-electrodes and between the through-via structures; and bump structures below the second dielectric layer and electrically connected to the through-electrodes and the through-via structures.
Juhyeon Kim, Ilhwan Kim, Sunkyoung Seo, Chajea Jo
Filed: 5 Apr 23
Utility
Semiconductor Package
4 Jan 24
A semiconductor package includes: a redistribution structure having a first surface and a second surface and including a plurality of redistribution layers, the plurality of redistribution layers including first and second redistribution layers adjacent to the first and second surfaces, respectively,; a semiconductor chip disposed on the first surface; a frame including a wiring structure connected to a first redistribution via of the first redistribution layer; and UBM layers disposed on the second surface and having a plurality of UBM vias.
Youngbae Kim, Seoeun Kyung
Filed: 30 Jun 23
Utility
Interconnection Structure and Semiconductor Package Including the Same
4 Jan 24
Disclosed are interconnection patterns and semiconductor packages including the same.
Junyun Kweon, JUMYONG PARK, JIN HO AN, Dongjoon Oh, JEONGGI JIN, HYUNSU HWANG
Filed: 18 Sep 23
Utility
Semiconductor Package
4 Jan 24
A semiconductor package includes: a package substrate including a first region, a second region, a first surface, and a second surface opposing the first surface; a semiconductor chip mounted on the package substrate; a pad including a first sub-pad, which is disposed on the second surface of the first region, and a second sub-pad, which is disposed on the second surface of the second region and includes a solder ball recess; and a solder ball disposed on the second surface, wherein the solder ball includes a first sub-solder ball and a second sub-solder ball, wherein the first sub-solder ball is connected to the first sub-pad, and the second sub-solder ball is connected to the second sub-pad, wherein the second sub-solder ball includes a first portion and a second portion, wherein the first portion is disposed in the solder ball recess, and the second portion is disposed on the first portion.
Seon HEO
Filed: 5 May 23
Utility
Method of Fabricating a Semiconductor Package
4 Jan 24
A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.
Myungsam KANG, Youngchan KO, Taesung JEONG
Filed: 12 Sep 23
Utility
Interposer and Semiconductor Package Including the Same
4 Jan 24
An interposer includes a base layer including a first surface and a second surface that are opposite to each other.
Yukyung PARK, Minseung YOON, Yunseok CHOI
Filed: 11 Sep 23
Utility
Semiconductor Packages
4 Jan 24
A semiconductor package includes a first redistribution structure including a first redistribution layer; a semiconductor chip on a first surface of the first redistribution structure and including a connection pad electrically connected to the first redistribution layer; an encapsulant that surrounds at least a portion of the semiconductor chip; a second redistribution structure on the encapsulant and including a second redistribution layer; a through-via structure that extends through the encapsulant and electrically connects the first redistribution layer to the second redistribution layer; an organic material layer between the through-via structure and the encapsulant and having an elongation rate greater than an elongation rate of the encapsulant; and a bump structure on a second surface of the first redistribution structure.
Jingu Kim, Yieok Kwon, Sangkyu Lee, Taesung Jeong
Filed: 9 Mar 23
Utility
Semiconductor Device Including Dummy Pad
4 Jan 24
A semiconductor device may include a first substrate including device and edge regions, a first insulating structure on the first substrate, first metal pads and first dummy pads at the uppermost end of the first insulating structure, a second insulating structure on the first insulating structure, second metal pads and second dummy pads at the lowermost end of the second insulating structure, a first interconnection structure in the first insulating structure, electrically connected to the first metal pads and electrically isolated from the first dummy pads, and a second interconnection structure in the second insulating structure, electrically connected to the second metal pads, and electrically isolated from the second dummy pads.
INHYO HWANG, YOUNG LYONG KIM, HYUNSOO CHUNG
Filed: 10 Mar 23
Utility
Semiconductor Package
4 Jan 24
The reliability of stacked semiconductor packages may be improved via a semiconductor package including a first semiconductor chip including through silicon vias (TSVs) with respective upper conductive pads electrically connected to the TSVs, a second semiconductor chip on the first semiconductor chip with lower conductive pads on a lower surface of the second semiconductor chip, conductive bumps between the upper conductive pads and the lower conductive pads, and an interlayer adhesive layer between the first semiconductor chip and the second semiconductor chip.
Wonjung Jang, Jungseok Ahn
Filed: 3 May 23
Utility
Package Device Including Capacitor Disposed on Opposite Side of Die Relative to Substrate
4 Jan 24
A package device is provided.
Sangho LEE, Kihyun KIM, Sangyong PARK, Kwanghyun BAEK, Seungjae BAEK
Filed: 14 Sep 23
Utility
Semiconductor Device and Method for Fabricating the Same
4 Jan 24
There is provided a semiconductor device including an active pattern which includes a lower pattern extending in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction on a substrate, the lower pattern including a protruding pattern protruding from the substrate in the second direction, and a capping pattern being in contact with the protruding pattern on the protruding pattern, a first gate structure and a second gate structure which are disposed on the lower pattern and spaced apart from each other in the first direction, and a source/drain pattern which is disposed on the lower pattern and in contact with the sheet pattern, wherein a thickness of the capping pattern in a portion that overlaps the first gate structure is different from a thickness of the capping pattern in a portion that overlaps the second gate structure.
Dong Woo KIM, Jin Bum KIM, Sang Moon LEE
Filed: 25 Apr 23
Utility
Semiconductor Device
4 Jan 24
Taeyong Kwon, Yoonjoong Kim, Seungmin Kim, Dogeon Lee
Filed: 16 May 23
Utility
Image Sensor
4 Jan 24
An image sensor including: a first layer including a plurality of photodiodes arranged in a plurality of pixel regions in a first substrate, an optical region disposed on an upper surface of the first substrate, and an element region, wherein, in at least one of the plurality of pixel regions, the element region includes a first impurity region, a first transfer gate disposed between the first impurity region and the photodiode, a second impurity region isolated from the first impurity region, and a second transfer gate disposed between the second impurity region and the photodiode: and a second layer including a second substrate stacked with the first layer, wherein the second layer includes a first transistor connected to the first impurity region by a first contact, and a second transistor connected to the second impurity region by a second contact.
Eunsub Shim, Jungchak Ahn
Filed: 14 Mar 23
Utility
Image Sensor Package Including a Chip Stack Structure
4 Jan 24
An image sensor package includes a package substrate, a logic chip mounted on the package substrate and having a central region and an edge region, an image sensor chip mounted on the central region of the logic chip, a bonding wire electrically interconnecting the package substrate to the logic chip and bonded to the edge region of the logic chip, a dam structure disposed in the edge region of the logic chip to cover a portion of the bonding wire, a cover glass disposed on the dam structure, and an encapsulation structure encapsulating the bonding wire on the package substrate.
KYONGSOON CHO
Filed: 21 Jun 23
Utility
Image Sensors with Light Channeling Reflective Layers Therein
4 Jan 24
An image sensor includes a two-dimensional array of image sensor pixels, which are formed in a semiconductor layer.
Kyungho Lee, Hyuk An, Hyuk Soon Choi
Filed: 15 Sep 23
Utility
Semiconductor Device
4 Jan 24
A semiconductor device includes an active pattern having a lower pattern, and a plurality of sheet patterns spaced apart from the lower pattern in a first direction; first and second structures disposed on the lower pattern, wherein the first and second structures are arranged and spaced apart from each other in a second direction; a source/drain recess defined between first and second gate structures; and a source/drain pattern filling the source/drain recess, wherein the source/drain pattern includes a stacking fault spaced apart from the lower pattern.
Soo Jin JEONG, Myung Gil KANG, Tae Gon KIM, Dong Won KIM, Ju Ri LEE
Filed: 25 Apr 23
Utility
Semiconductor Devices
4 Jan 24
A semiconductor device includes an active region extending in a first direction on a substrate; a plurality of channel layers on the active region and spaced apart from each other in a vertical direction that is perpendicular to the first direction; a gate structure on the substrate, the gate structure intersecting the active region and the plurality of channel layers, extending in a second direction crossing the first direction, and respectively surrounding the plurality of channel layers; inner spacer layers on both sides of the gate structure in the first direction, and on respective lower surfaces of the plurality of channel layers; a protective layer in contact with the inner spacer layers, the plurality of channel layers, and the active region; and a source/drain region on the active region, on at least one side of the gate structure, and in contact with the inner spacer layers.
Junbeom PARK, Sangwon BAEK, Yunsuk NAM
Filed: 1 Jun 23
Utility
All-solid-state Secondary Battery and Method of Preparing the Same
4 Jan 24
An all-solid-state battery including a cathode including a cathode active material; an anode including an anode current collector, a first anode active material layer, and a second anode active material layer; and a solid electrolyte arranged between the cathode and the anode, wherein the first anode active material layer is arranged adjacent to the solid electrolyte and comprises M1-M2Ox, Li-M1-M2Ox, or a combination thereof, wherein the first metal and the second metal are each independently at least one element that reacts with lithium to form a lithium alloy or compound, x>0, the second anode active material layer is arranged between the anode current collector and the first anode active material layer and includes a second anode active material, and the second anode active material includes a carbon-containing anode active material, or a carbon-containing anode active material, and at least one of a metallic or metalloid anode active material.
Jusik Kim, Sewon Kim, Yongsu Kim, Ryounghee Kim, Myungjin Lee
Filed: 28 Jun 23
Utility
Cathode Active Material, Cathode and Lithium Secondary Battery Comprising Same, and Preparation Method Therefor
4 Jan 24
Sangbok Ma, Joonhee Kim, Sungjin Lim, Valentina LACIVITA, Yongwoo Shin, Taeyoung Kim
Filed: 29 Sep 21
Utility
Modem Supporting Digital Pre-distortion, Antenna Module, and Method for Operating Same
4 Jan 24
An antenna module may include antennas, RF chains connected to the antennas, a splitter/combiner connected to the RF chains, a mixer configured to upconvert an IF signal input to the antenna module into a transmission RF signal and output the upconverted signal to the splitter/combiner and/or to downconvert a reception RF signal which is a combination of signals from the RF chains provided from the splitter/combiner, a plurality of first couplers connected between the RF chains and the antennas, a second coupler for measuring a magnitude corresponding to a transmission RF signal before split by the splitter/combiner and/or the reception RF signal combined by the splitter/combiner, and a power detector configured to provide a plurality of magnitudes of a plurality of signals from the plurality of first couplers and a magnitude of a signal from the second coupler.
Namjun CHO, Hyosung LEE, Junghwan SON, Hyoseok NA
Filed: 30 Jun 23