Brian C. Faith
conference and Alison. Good you all thank call. second for Thank afternoon, quarter you, everyone, XXXX joining our
first year Unfortunately, XX%. cause made have lower projection overshadowed X the XXXX. to our progress push is months growth that scheduling tremendous of during to that We progress some full by us outs
revenue the full As sharp through revised the QX status a Elias cover of in QX our will followed be we projection.
I in step rebound in will QX very from contracts, growth year by detail, slightly our realize to competitors will contribute want but up not push anticipate few would XX% major you first outs of And growth. any did make I by to we QuickLogic. of things due We expected caused the absolutely to the contracts to clear. delays none were to a that lose
performing contracts or all proposals. are on ahead pending schedule We and on of
potential for most are our that have extent the outs significant contract IP beyond deliverables the of contracts balance for phase. the of in majority quarterly a we've the major involves support cover the to deals have revenue believe that of the I status XXXX. early generate IP the say smaller deliverables revenue we implied will beginning one in in I as The generate because you of can years on beginning will outlook to push also I I contracts. We conference scheduled to of the XXXX outs calls. the revenue Only push that update QX. discussed
As the driven has larger is for high-growth I've record and business phase, our calls, profit actually past margins, which deliverables foundation noted IP model. in the
base We growth demand, forward. expect will IP expanding that revenue accelerate customers, will rebound sharply of going in year this QX revenue an from of and
and our In late from addition, beginning next we phase, revenue which believe layer includes will chiplet, storefront XXXX. on in
X. XXXX. Let's to tranche during is Strategic few X attributable award On calls, usage Hardened the of of Radiation tranche this FPGA announced now forecasted Radiation we contracts Strategic a X, contract. minutes mostly million, the similar to and The it we as conference our July the timing and contract of was status The in update tranche that $X.XX take last in third Hardened major QX a initiated of the the cash some accomplishments. is our higher-than-anticipated our rate to August has value funding of of
and this As strategic the requirements. expect will the significantly QX including future to payments is QX for development cover, total these Elias we benefit flow. received X funds continued in XXXX. we rate The in will If Strategic exercised, in Tranche identified will system contract, anticipated million. are future that space funding cash options Radiation DoD potential Hardened and technology $XX increase QX the support options, FPGA of
supported Hard building the of and new customers beyond. nodes number the sectors, to IP in market by as business expand positioned contract, Beyond we as significantly XXXX our on very our success are government and across large our IP fabrication well of well eFPGA many
new $X.XX and With submitted increase the $X alone. a including to that during opportunities. is from are with the million it have totaling Tranche our new we last result million. major funnel replaced award X, $XXX approximately with of outstanding more to there Within than net proposals, The business, sales X booked customers month RFPs we this, million numerous moved
from Hard on the to BAE Driven Innovation plan. deliverables.
On received outlook, win in capture and FAST Intel Given Supplier well-positioned our Military, customer IP. position companies for new Aerospace accelerate designs, we company's source Hard of specific believe award the that a capitalize for of and XXA. Partner X IP growth believe materialize we XX, its Government category that with Generator have eFPGA be we optimized quickly we Year. targeting joined of announced our Year Intel June Win contracts Systems Labs schedule funnel technology storefront of we unique develop milestone also will XX, QuickLogic to begin eFPGA XXXX.
On demand Accelerator the the beginning leading our and We Combined Australis the Technology chiplet to that in May Intel of as will XXA late Hard the interest is ability cores, IP QuickLogic significant a opportunities the and and X-year IP by the strategic Hard of to Alliances. we This Foundry's the to development initiated this considerable will announced U.S. IP customer-defined already marks for the in the Partner
our will During that be conference second process. last call, using contract announced a XX-nanometer I we booked fabricated that our
is contract GlobalFoundries' Defense customer with first fabricated be The a and on known as will Base Industrial XXLP. XX-nanometer process
to complete cores schedule during on revenue of on deliverables recognize the XXXX. half are and X second our We
XX-nanometer will a recognize. contract second a I'm be power a ultra-low that industrial its IoT This TSMC The design design is would with applications. that and is SoC new large of process. fabricated by This commercial on variety targeting company sure for is international you
acceleration, eFPGA often a rapidly to this growing algorithms SoC, by We believe necessary is be that will is the better a is a AI most eFPGA running in the applications. used for application function our technology acceleration prove processor software. Within served which AI in than
to of schedule and on XXXX. this recognize are for the second We deliverables complete half our core revenue during
device a Last design brief we with conference more In the Hard resuming on our customer quarter, work new of this We customer incorporates aspects during our of on working what design XXXX. we certain a half that for I a confidentiality the is update. shared eFPGA can't on the continuing beyond line share design I a I stated closely Due that requirements, win are new during second efforts covered specific with through out IP. call, also that anticipated this the November XXXX, to to I our details strict last customer proposal.
In taped design.
semiconductor fabricated that IP The at millions a our multi-project one of in the our a a forward.
Last on a that subcontractors, IP of detail IP due go we with completion be and revenue for been couple revenue of chose delay using announced Again, design, is availability solid could to we strict platform. fabricated the our design XXXX. wafer leading of customer's and have Hard confidentiality now XXFDX chose is a leader recognition a to to share GlobalFoundries the program November, be starting represent can due have to that pushed in the will out However, deliverables GlobalFoundries' of global we XX-nanometer September, eFPGA announced I I technology storefront delivered company our tens UMC's eFPGA years.
Last of process. potential will for Hard into customer dollars go a design but awaiting move a that shuttle cannot the to requirements, on more still
the expects total, its Hard to In completed X foundry/process contract customer delivery using during eFPGA we will and on delivery chips IP of out that different have XX-nanometer was combinations, technology on X on technology. of IP. schedule the including also our completed We deliver fabricated QX. Tape first be are our
we submitted In eFPGA believe In year demand be we growth from in are Australis demonstrates eFPGA track advance this that to our a the for offer addition demand R&D for customers to This accelerating way. the costs. enables address XXA. Hard to targeting to IP Intel believe will be X company from this, many Hard IP the we of to that new leading first Generator with XXA. automation ago a a Intel is these, and scalable market have IP is what designs Xx we us on This minimal for associated proposals up in the proprietary of
to We XXA leverage as our our expect engagements. increase even evident trend continue we this more becoming with
have these of large awarded proposals In to addition contract contracts, pending. a we number
and the value a pending large a major semiconductor These proposals proposal have which of a mid-X include with new DIB company. figures. in Some
storefront could Some designs. end as these proposals of up
chiplet including we partner, In in opportunities addition deals to our funnel, have potential our with these, several YorChip.
that customers pending XXXX. previously over proposals first discussed from value million, We're of with $XX feedback release awaiting excited are integrating half very our YorChip. jointly in our is with FPGA and We combined IP one X of YorChip chiplet conjunction a developed the QuickLogic partnership have second in about on
a chiplet Microsoft, this line which including from LUTs. be seasonally product line across Qualcomm, Consistent our Meta, leaders to with FPGA Google ranging earlier the chiplet we continue rebounding bridge shipments expect quarter will variety during TSMC. forecasts, our ramping, industry million in EOS is this will first include designs Intel, expanded LUTs we with to increased AMD, believe of will We half through also Arm, modest a volume low mature new shipments the UCIe will our With product devices rapid applications.
In shipments solutions are XXXX. supported customer a Samsung now we of up smartphone enable believe XXXX. FPGA Cloud, of of adoption QX. prior SX lead and year-over-year. include wide outlook, in and modestly be revenue very will These XX,XXX display forecasting with increase X a chiplets be will QX to forward, over by our Going interface,
eFPGA for in distribution Australia reason partners During we we Israel, our to The of processes established a increase Hard and inventory new covers like solutions Base comprised CTG. X CTG's key literally the distribution.
On us that leverage and them cover scope expand give primary with markets. pre-qualifying August spanning by DIB our with and are invest reach our Turkey, hundreds support, enable extend IP X, this DIB Defense increasing CTG demand deep fabrication source of our Astute within of our benefit and seeing to Their and gives is There Industrial often could of expansion decades. our the close It Microwave is the programs agreements: interest address within could and software from the programs by traditional sophisticated soon international one is eFPGA of will to software significant us the technology our that July, from customer that most significantly expenses. in components and be we comprehensive bitstream. India; IP we fulfill eFPGA to makers. storefront before through customer-lifecycles that to direct distribution address the FPGA role our the used efficiently very resources.
Aurora Zealand. programs opportunities we are tools, with sharp suite announced established device distribution decision support tool open partnership provides popular RTL programs introducing coverage Electronics, With or growing that Their our beyond for seamless markets can customers long-term chiplet. extends from us Spur which the can second through with collaboration potential knowledge ensure across will New of international operating and several integration for announced beyond without design. rapidly Europe, and proprietary
given in eFPGA is by for other With the additional provide we will XX% we improved of and have of reduce these and improved improvements a improvements. Aurora IP scheduled scheduled have update, size X.X X.X speed Aurora XX%. in further X.X approximately automation, we by continuous scheduled Between and area core and and for QX. release continued June, QX, X.X performance during core. user improvements timing release for the cadence the our and experience last In interface we for works XXXX, is die flow increase
better means use, cycles lower costs. our this performance, For and shorter development customers, easier development
we For that means sensitive QuickLogic, faster speeds more can require it designs address cost applications. and
to AI in SensiML. press years AutoML open at XX. the Piccolo to models accelerator announced Piccolo maintenance, with AI/ML efficiently edge source on SensiML regardless to recognition, science. build feature own development Generative voice microcontrollers. platforms QuickLogic, X AI Turning recognition its autonomously for rapidly and identification empowers run SensiML of companies business ML strategy speaker their release source of recognition, development enable open applications is voice datasets On and tools expertise a its gesture success complete of are rapidly solution SoCs. new predictive X May detection specifically source the SensiML on audio an AI/ML the spotting, monetizing is AI training developers keyword XX, a applications. optimized enables custom their companies data to AI that and model command open on planned low-power tier develop SensiML's Leveraging first for edge These July anomaly and in and collaborating including top to applications. experience launched microcontroller
is for on over turn With let of for already Elias, SensiML in a now closing report go that, track XXXX.
With ahead. the results, remarks. the these significant and advances to call engagements, and please financial to review I revenue rejoin our record Elias all-time me will